Senior Staff Engineer, Physical Design - NoC

Job Title

Senior Staff Engineer, Physical Design - NoC

Role Summary

Senior Staff Physical Design Engineer responsible for end-to-end physical implementation of NoC and Uncore subsystems from RTL to GDSII. The role bridges architecture, RTL and backend implementation to deliver high-bandwidth, PPA-optimized IP for multiple products.

Experience Level

Senior level. Requires 10+ years of hands-on physical design implementation experience.

Responsibilities

Primary responsibilities include ownership of physical implementation, cross-layer co-design, and methodology improvements for large, high-bandwidth interconnects.

• Lead full-flow physical implementation for complex NoC and Uncore subsystems (synthesis, place & route, signoff).
• Drive architecture/RTL/physical-design co-design to resolve physical bottlenecks early.
• Solve NoC-specific challenges: long-distance timing, repeater/pipeline insertion, top-level clock distribution.
• Define top-level floorplanning, macro placement, hierarchical partitioning, and pin assignment to optimize data flow.
• Optimize implementations for aggressive PPA targets across technology nodes.
• Collaborate with architecture, RTL, and power teams to influence micro-architecture and achieve closure.
• Develop and improve physical-design flows, automation, and hierarchical implementation methodology.
• Mentor and provide technical leadership to junior engineers.

Requirements

Must-have skills and experience to perform the role.

• 10+ years of hands-on physical design implementation experience focused on large, complex designs.
• Proven physical-design experience with NoC, coherent hubs, or complex memory subsystems and high-bandwidth bus routing.
• Deep expertise in top-level integration, hierarchical P&R methodologies, and global timing closure.
• Strong problem-solving skills with experience optimizing designs to meet aggressive PPA targets.
• Practical experience with Synopsys and/or Cadence synthesis, P&R and signoff tools (RTL to GDSII flow).
• Ability to read RTL and work across abstraction layers to enable architecture/design/implementation co-design.
• Proven cross-functional collaboration and leadership; mentoring experience preferred.
• Excellent communication and documentation skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.