Senior Staff Engineer, Physical Design

Job Title

Senior Staff Engineer, Physical Design

Role Summary

Lead physical design and methodology efforts for high-performance processor/ASIC products targeting server and networking applications. Work with local and global teams to implement full-chip designs and improve design flows and automation.

This role focuses on physical implementation (place and route, timing, verification), design integration, and methodology development for complex, tape-out scale chips.

Experience Level

Senior. See Education Requirements for degree/experience equivalencies and acceptable substitution by professional experience.

Responsibilities

Key responsibilities include implementation, integration, automation, and mentorship.

• Lead physical implementation activities: place-and-route, static timing analysis, and physical verification for large designs.
• Integrate full-chip and sub-hierarchy blocks; drive design convergence with RTL, analog, and other teams.
• Support multi-voltage and low-power implementation and signoff flows.
• Drive assembly and design closure with RTL teams toward tape-out.
• Develop and improve methodology and flows from RTL to GDS.
• Automate data extraction and productivity tasks using scripting (Shell, Python, TCL, Perl).
• Provide technical direction, coaching, and mentoring to junior engineers.

Requirements

Must-have technical skills and practical experience; degree details are in Education Requirements below.

• Expertise in full-chip and sub-hierarchy integration and tape-out of large digital designs.
• Strong understanding of RTL-to-GDS flows and digital design implementation.
• Proficient scripting skills (Perl, TCL, Python, Shell) for automation and data extraction.
• Knowledge of Verilog and digital logic; familiarity with computer architecture concepts.
• Effective communicator and able to work in cross-disciplinary teams.
• Nice-to-have: experience with multi-voltage/low-power design techniques and Cadence Innovus.
• Other: role may require eligibility for export-controlled technology access; candidates may be subject to export license review.
• Accommodations: applicants needing reasonable accommodation may contact Marvell HR Helpdesk at TAOps@marvell.com.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with roughly 3–5 years of relevant experience; or a Master's/PhD in a related field with roughly 2–3 years of relevant experience. Equivalent professional experience may be accepted in lieu of a formal degree. Fields referenced include Computer Science and Electrical Engineering.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.