Senior Staff Engineer, Physical Design
RenesasJob Title
Senior Staff Engineer, Physical Design
Role Summary
Lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. Work with cross-functional teams to develop and scale closure methodologies, flows, and automation while mentoring physical design engineers.
Experience Level
Senior - typically 7+ years of professional experience in physical design with a focus on subsystem-level closure for hierarchical SoCs.
Responsibilities
Key responsibilities include:
- Lead block- and subsystem-level physical design closure: timing closure, congestion mitigation, power integrity, and overall implementation quality.
- Collaborate with SoC-level physical design teams on clocking strategies, floorplanning intent, and integration requirements (without owning SoC-level execution).
- Apply clocking methodologies to ensure subsystem clock domains integrate into the SoC clock architecture.
- Develop, refine, and scale subsystem closure methodologies, flows, and automation to improve predictability and execution efficiency.
- Mentor and guide physical design engineers on best practices and methodology adoption.
- Work cross-functionally with RTL, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure.
- Identify, assess, and mitigate physical design risks and coordinate solutions with SoC teams.
Requirements
Must-have technical skills and experience:
- 7+ years of experience in physical design, focused on subsystem-level closure for hierarchical SoCs.
- Expertise in timing closure, constraint management, congestion analysis and resolution, and power-aware physical implementation.
- Solid understanding of SoC-level floorplanning and clocking methodologies to enable effective collaboration with SoC teams.
- Hands-on experience with industry-standard tools such as Synopsys ICC2/Fusion Compiler/PrimeTime or Cadence Innovus/Tempus/Certus and signoff/analysis platforms.
- Proficiency in scripting and automation using Tcl, Python, and/or Perl.
- Deep knowledge of end-to-end SoC design flows and low-power design techniques.
- Demonstrated ability to mentor engineers and improve methodologies and automation.
Education Requirements
BTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
