Senior Staff Engineer - Microcontroller Sub-System Design

Job Title

Senior Staff Engineer - Microcontroller Sub-System Design

Role Summary

Lead technical architect and hands‑on designer for microcontroller sub-system IP used across SoCs. The role drives micro‑architecture, RTL implementation quality, and subsystem-level tradeoffs for embedded processing features such as security, power management, and system integration.

Work within a cross‑functional ASIC team to deliver high‑performance, low‑power microcontroller subsystems that meet product requirements across IoT, Mobile, Auto, XR and Compute programs.

Experience Level

Senior - role expects senior/technical‑lead level experience. The posting describes 10+ years of ASIC design experience as a role expectation; minimum qualification text also documents typical degree-plus-experience combinations and allows equivalent experience.

Responsibilities

You will provide technical leadership and execute on design, verification support, and integration tasks across the microcontroller sub-system.

• Drive micro‑architecture decisions for simple and complex digital blocks; make tradeoffs across area, power, and performance.
• Lead RTL development using industry best practices for multi‑clock, high‑frequency, low‑power, and low‑latency designs.
• Own root‑cause analysis and resolution during design and lead post‑silicon bring‑up activities with cross‑functional teams.
• Create and maintain design documentation; lead architecture and design reviews to ensure maintainability and reuse.
• Optimize designs for area, power, and performance while balancing product and implementation constraints.
• Collaborate with DFT, Implementation, Verification, Emulation, and Firmware teams and mentor junior engineers.

Requirements

Must‑have skills and experience to perform the role; qualifications and degree expectations are summarized separately below.

• Must have: Significant ASIC design experience (senior/lead level; posting cites 10+ years) with ownership of complex subsystem or SoC deliverables.
• Proven delivery of complex digital logic blocks and subsystems in high‑performance, low‑power contexts.
• Strong understanding of processor/microcontroller system design and ISAs (examples cited: ARM THUMB, RISC‑V).
• Deep experience with multi‑power‑domain and multi‑clock‑domain designs and their verification challenges.
• Expertise in RTL development and familiarity with industry‑standard digital design tools and flows.
• Experience leading debugging, root‑cause analysis, and post‑silicon bring‑up across cross‑functional teams.
• Proficiency in scripting/automation (e.g., Python or Perl) to support design and verification workflows.
• Proven technical leadership: mentoring, influencing methodology, and driving execution on complex programs.
• Nice to have: Familiarity with DFT, emulation flows, and challenges of lower node technologies; experience with vendor tools (example: Cadence) and system integration practices.

Education Requirements

Degree options cited: Bachelor's, Master’s, or PhD in Science, Engineering, or a related field. Minimum‑qualification text lists: Bachelor’s degree plus 2+ years of ASIC design/verification/integration experience; OR Master’s plus 1+ year; OR PhD. The posting also states applications with equivalent experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.