Senior Staff Engineer, Layout Design

Job Title

Senior Staff Engineer, Layout Design

Role Summary

Lead physical layout development for advanced memory IP (SRAM, ROM, eDRAM and emerging memories) across advanced and mature process nodes. Work with circuit designers, foundries, and product teams to deliver manufacturable, high-yield memory designs to production.

Focus areas include layout architecture, manufacturability, automation, and mentoring engineering teams to raise execution quality.

Experience Level

Senior — typically 10+ years of hands-on experience in custom physical layout design, with significant memory IP and tapeout experience.

Responsibilities

Accountabilities for the role include technical leadership of layout execution, methodology, and tooling.

• Lead complete physical layout development for advanced memory IP across nodes (including leading-edge nodes such as 3nm and mature technologies).
• Drive layout architecture decisions: bit-cell topology, array organization, peripherals, power distribution, and full memory integration.
• Define and implement layout methodologies to improve area efficiency, performance, power, manufacturability, and yield.
• Resolve complex DRC, LVS, ERC, and EMIR issues in dense memory structures and work directly with foundry teams when rules or models require clarification.
• Lead RC extraction, parasitic analysis, and signal-integrity work; collaborate with circuit designers to close timing, power, and reliability on critical paths.
• Develop layout automation, generators, validation flows, and scripting tools to accelerate execution and improve design quality.
• Mentor staff and senior layout engineers, review critical design decisions, and establish best practices across projects and sites.

Requirements

Must-have technical skills and demonstrated experience.

• Typically 10+ years of hands-on experience in custom physical layout design with deep expertise in memory IP development.
• Proven track record delivering memory IP (SRAM, ROM, eDRAM) in production silicon across multiple advanced technology nodes and tapeouts.
• Deep expertise in memory layout: bit-cell design, array structures, sense amplifiers, decoders, redundancy circuits, I/O, and peripheral blocks.
• Proficiency with layout tools such as Synopsys Custom Compiler, Cadence Virtuoso, or equivalent custom-design platforms.
• Advanced understanding of foundry design rules, DRC/LVS closure methodologies, reliability requirements, and EMIR validation.
• Proven ability to lead technical decisions, mentor engineers, and set methodologies used across teams.
• Nice-to-have: experience developing layout automation, scripting solutions, generators, or methodology improvements.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or a related technical discipline.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.