Senior Staff Engineer, Hardware & Silicon Validation

Job Title

Senior Staff Engineer, Hardware & Silicon Validation

Role Summary

Senior engineer responsible for post-silicon validation and lab bring-up of PCIe/Ethernet PHYs and related high-speed interfaces. The role focuses on PHY/PCS layer testing, high-speed signal characterization, firmware/hardware debugging, and cross-functional/customer support for production silicon.

Experience Level

Senior-level. Typical experience: 8–10 years in high-speed I/O testing, debugging and validation (or 6–8 years with an advanced degree).

Responsibilities

Primary duties involve hands-on silicon validation, test plan execution, and cross-team issue resolution.

• Define, document, execute and report PHY validation/test plans for in‑house PCIe/Ethernet IP in a post-silicon environment.
• Perform lab-based silicon bring-up, unit testing and system-level validation for physical and PCS layers, and extend testing to protocol layers as needed.
• Characterize high-speed signals (eye diagram, jitter, BER) and analyze results using oscilloscopes, BERTs, network analyzers and protocol/logic analyzers.
• Diagnose failing tests using diagnostics, firmware/software tools and hardware analyzers; lead technical discussions to drive resolutions.
• Collaborate with cross-functional teams, external vendors and customers to debug post-silicon or field issues.
• Develop and maintain validation automation and data analysis scripts/tools.

Requirements

Must-have technical skills and experience for immediate contribution.

• Strong understanding of high-speed SERDES, equalization techniques and PCIe protocols.
• 8–10 years of practical experience with high-speed I/O testing, debugging and validation (hands-on lab work, system bring-up, system testing).
• Proven hands-on lab skills and experience with test equipment used for SERDES characterization (oscilloscopes, BERT, network analyzer, etc.).
• Experience developing validation automation and performing data analysis with scripting languages (Python, MATLAB, or similar).
• Strong analytical and problem-solving skills, with effective written and verbal communication in English.
• May require eligibility to access export-controlled technology; non-U.S. applicants may be subject to export license review.

Nice-to-have / preferred:

• Working knowledge of PCIe, Ethernet and/or SAS/SATA SERDES.
• Experience with physical and protocol layers (PIPE I/F, PCS, MAC) of high-speed interfaces.
• Ability to read board schematics and board layout; board-design familiarity.
• Knowledge of SERDES modeling techniques.

Education Requirements

Bachelor of Science in Electrical Engineering (with ~8–10 years relevant experience) or Master of Science in Electrical Engineering (with ~6–8 years relevant experience). Relevant domains: pre/post-silicon validation, stress and PVT testing. Equivalent practical experience may be considered.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.