Senior Staff Engineer, Digital IC Design
ASIC engineer on the Central Engineering AMS‑IP team responsible for post‑RTL digital implementation for SerDes PHY and other analog/mixed‑signal IP. Primary mission: drive synthesis, timing closure, DFT and ECOs to deliver block and chip‑level solutions.
Works with analog and digital design teams to integrate SerDes IP across product lines and supports pre‑ and post‑silicon activities.
Senior — 6+ years of relevant post‑RTL/ASIC design experience.
Key responsibilities include implementation, verification support, and methodology improvements.
Must‑have technical skills and practical experience.
Nice‑to‑have:
Master's degree and/or PhD in Electrical Engineering, Computer Science, or a related technical field (as stated in the posting).
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
