Senior Staff Engineer, DFT

Job Title

Senior Staff Engineer, DFT

Role Summary

Member of the India DFT team within the Data Center Engineering Business Unit responsible for developing and delivering DFT architecture, methodology and design solutions for complex ASIC/SoC projects. The role supports customer DFT requirements for Custom and Compute businesses and collaborates across RTL, synthesis, and physical design teams.

Primary focus areas include scan and test flow development, ATPG and compression, pre-silicon validation, and post-silicon bring-up for high-complexity SoCs.

Experience Level

Senior — typically 7 to 10 years of experience in DFT for complex ASIC/SoC designs (posting also references 8–10 years in one place).

Responsibilities

Key responsibilities include implementation, validation, and integration of DFT solutions across the chip design flow.

• Develop and integrate scan insertion, MBIST, OCC, boundary-scan and hierarchical SDC flows.
• Drive ATPG pattern generation, compression techniques, gate-level simulation (GLS), and test retargeting.
• Collaborate with RTL, synthesis, STA and physical design teams to ensure DFT integration and constraints alignment.
• Perform SpyGlass DFT checks and address design-for-testability issues.
• Perform pre-silicon validation of DFT features and support post-silicon bring-up and debug.
• Optimize test methodologies for coverage, cost, and yield improvement.
• Automate flows and tooling using scripting for repeatable DFT flows and validation.

Requirements

Must-have technical skills and experience; degree requirements are summarized separately under Education Requirements.

Must-have:

• Proven experience with scan insertion and ATPG tools (Synopsys, Cadence, Mentor).
• Hands-on experience with MBIST and OCC validation flows.
• Experience managing hierarchical DFT and SDC constraints across blocks.
• Knowledge of SSN design and IEEE 1687 (IJTAG) standards for embedded instrumentation.
• Familiarity with SpyGlass DFT rules and design-for-testability checks.
• Strong fundamentals in digital and logic design; practical understanding of RTL, synthesis, STA and physical design impacts on testability.
• Scripting and automation experience (TCL, Perl, Python, Shell, or similar).
• Experience with silicon bring-up and debug.
• Good problem-solving, communication, and cross-functional collaboration skills.

Nice-to-have:

• Experience optimizing ATPG compression and retargeting strategies for large designs.
• Familiarity with gate-level simulation workflows and advanced test compression techniques.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI or a related field. The posting specifies 7–10 years of DFT experience for complex ASIC/SoC designs (one statement references 8–10 years).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.