Senior Staff Engineer - Design Verification (SerDes/PHY/AMS/Mixed-Signal)

Job Title

Senior Staff Engineer - Design Verification (SerDes/PHY/AMS/Mixed-Signal)

Role Summary

Hands-on verification engineer responsible for block- and subsystem-level verification of mixed-signal AMS and high-speed SerDes/PHY IP. Part of the Central Engineering AMS IP team delivering reusable verification solutions for SoCs and platforms to enable first-time-right silicon and reduced integration risk.

Focus on execution excellence, verification convergence, system-level validation, and improving verification flows across advanced process nodes.

Experience Level

Senior — typically 5 to 9 years of relevant verification and/or AMS/mixed-signal design experience.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification for AMS and SerDes IP with clear ownership of assigned areas.

• Drive block- and subsystem-level verification for AMS and high-speed SerDes/PHY IP.
• Develop and implement verification plans, testbenches, and UVM-based environments using SystemVerilog.
• Integrate and use verification IPs (VIPs) and maintain regression suites.
• Perform coverage analysis and manage regression flows.
• Debug issues across multiple abstraction layers and coordinate with designers, firmware, and system teams.
• Communicate progress and technical findings clearly; propose incremental improvements to testbenches and flows.

Requirements

Must-have skills and experience for this role.

• Strong hands-on experience with SystemVerilog and UVM.
• Experience in verification and/or AMS/mixed-signal design environments with focus on SerDes/PHY.
• Working knowledge of SerDes or PHY architectures and register modeling/firmware interaction.
• Experience integrating or using verification IPs (VIPs).
• Familiarity with regression management, coverage analysis, and multi-layer debug.
• Demonstrated ownership, attention to quality, and clear communication skills.

Nice-to-have:

• Exposure to AMS verification tools and modeling techniques.
• Experience with link training, calibration logic, or DSP–analog interaction.
• Basic exposure to GLS, low-power verification, or post-silicon debug.
• Interest or experience in automation, scripting, and productivity improvements.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related technical field. The posting specifies 5–9 years of experience in verification and/or AMS/mixed-signal design environments for this role.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.