Senior Staff Engineer — Design Verification (SerDes / PHY / AMS)

Job Title

Senior Staff Engineer — Design Verification (SerDes / PHY / AMS)

Role Summary

Lead end-to-end verification for complex SerDes, PHY and AMS/mixed-signal IPs across advanced process nodes. Work within Central Engineering AMS IP to deliver reusable verification solutions that reduce integration risk and enable first-pass silicon success.

This is a hands-on senior engineering role combining deep technical ownership, cross-team collaboration (Design, Architecture, Firmware, Silicon), and mentoring responsibilities.

Experience Level

Senior-level — typically 8–12 years of hands-on experience in verification and/or AMS systems.

Responsibilities

The role is responsible for technical leadership and execution of verification tasks from planning through sign-off.

• Drive end-to-end verification ownership for SerDes, PHY and mixed-signal IPs across advanced nodes (5nm, 3nm, 2nm).
• Lead verification of high-speed interfaces including SerDes, PCIe, Ethernet, DDR, D2D and PAM4/PAM2 designs.
• Define and execute verification plans covering calibration, link training, power modes, analog-digital interaction, and firmware-driven flows.
• Debug and resolve complex issues spanning RTL, AMS models, firmware, VIPs, and system-level behaviors.
• Drive coverage closure, regression stability, and sign-off readiness to high quality standards.
• Own or co-own gate-level simulation, power-aware verification, CDC/RDC validation, and timing-aware checks.
• Collaborate with Design, Architecture, Firmware and Silicon teams to mitigate early risks and ensure alignment.
• Contribute to verification infrastructure, checkers, automation, and reusable frameworks.
• Mentor junior engineers and act as a technical role model within the team.
• Identify and implement productivity and quality improvements, including automation or AI-assisted verification tools.

Requirements

Must-have technical skills and qualifications; differentiators listed as nice-to-have.

• Must-have: 8–12 years of hands-on experience in verification and/or AMS systems.
• Must-have: Strong expertise in SystemVerilog, UVM and modern verification methodologies.
• Must-have: Deep understanding of SerDes/PHY architectures and AMS/mixed-signal verification.
• Must-have: Experience with calibration and link training flows, register models and firmware interaction.
• Must-have: Experience integrating and using industry VIPs (Synopsys, Cadence, Siemens/Mentor, Avery).
• Must-have: Proven ability to debug issues across multiple abstraction layers and a solid understanding of system-level trade-offs.
• Must-have: Eligible to access export-controlled technology and information as required by applicable U.S. export control laws; non-U.S. applicants may be subject to export license review.
• Must-have: Interview policy: use of AI tools during interviews is prohibited and may result in disqualification.
• Nice-to-have: Experience across multiple technology nodes and IP generations.
• Nice-to-have: Contributions to verification methodology improvements or reusable infrastructure.
• Nice-to-have: Exposure to post-silicon debug and silicon correlation.
• Nice-to-have: Participation in technical forums, papers, or conferences (e.g., DVCon, VLSI-D).

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.