Senior Staff Engineer, Design Verification

Job Title

Senior Staff Engineer, Design Verification

Role Summary

Lead verification of complex SoC and IP designs across networking, compute, storage, and infrastructure domains. Define verification strategy, develop test plans, and drive closure using advanced UVM methodologies, automation, and formal techniques.

Provide technical leadership to verification infrastructure and influence design-for-verification and architectural decisions that affect performance, scalability, and power efficiency.

Experience Level

Senior. Typical experience: Bachelor's + 5–10 years or Master's/PhD + 3–5 years (see Education Requirements for degree and experience combinations).

Responsibilities

Lead verification planning, execution, and debug for complex IP and SoC projects while mentoring engineers and coordinating cross-functional teams.

• Define verification strategies and test plans; develop scalable UVM-based environments and reusable frameworks.
• Drive RTL simulation, emulation, and post-silicon validation scope, timelines, and execution.
• Perform deep RTL and system-level debug and root-cause analysis across design, testbench, and integration layers.
• Write and apply SystemVerilog Assertions (SVA) and formal properties; use formal tools for property and equivalence checking.
• Improve automation, regression efficiency, and verification infrastructure; evaluate and adopt tools and methodologies.
• Manage verification milestones, risks, dependencies, and stakeholder communication to drive closure.
• Mentor junior engineers and promote verification best practices, reuse, and code quality.

Requirements

Must-have technical skills and proven experience to independently lead verification efforts and technical decisions.

• Strong digital design fundamentals: FSMs, combinational and sequential logic, and computer architecture.
• Experience applying industry protocols (AMBA, PCIe, Ethernet, memory coherency) in verification contexts.
• Expertise in UVM, constrained-random verification, functional coverage, and assertion-based verification (SVA).
• Proven RTL simulation, debugging, and root-cause analysis skills for SoC/ASIC design flows.
• Software and automation proficiency: C/C++ and scripting (Python, Perl, or similar) in Linux environments.
• Demonstrated ability to lead verification projects: planning, task distribution, tracking deliverables, and driving milestones to closure.
• Strong cross-functional collaboration, communication, and documentation skills.

Nice-to-have:

• Experience with emulation, post-silicon validation, and formal tool flows at system level.
• Prior influence on architecture and design-for-verification decisions for high-performance platforms.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of relevant professional experience; or a Master's degree or PhD in Computer Science, Electrical Engineering, or a related field with 3–5 years of relevant professional experience.

Expected base pay range (USD): 151,000 - 223,440 per annum.

Note: This position may require eligibility for access to export-controlled technology and/or a licensing review prior to employment.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.