Senior Staff Engineer, Design Verification

Job Title

Senior Staff Engineer, Design Verification

Role Summary

Senior hardware verification engineer responsible for developing and maintaining UVM-based verification environments for complex IP and SoC designs. Works within the verification team and collaborates with design, architecture, and firmware teams to ensure functional correctness and coverage closure.

Main mission: define verification plans from specifications, implement testbenches and tests, run regressions, debug RTL issues, and improve verification methodologies and automation.

Experience Level

Senior - typically 6–14 years of experience in digital verification as stated in the posting.

Responsibilities

Day-to-day responsibilities include designing verification environments, executing regressions, and driving defect debug to closure.

• Develop and maintain UVM-based verification environments, testbenches, test cases, and coverage models for IP and SoC designs.
• Analyze design specifications and create verification plans and scenarios.
• Execute regressions, monitor coverage metrics, and perform root-cause analysis of failures.
• Debug RTL issues in collaboration with design, architecture, and firmware teams.
• Contribute to verification methodology, tool automation, and continuous improvement.
• Participate in design and verification reviews and align verification timelines with project schedules.
• Mentor and guide junior verification engineers.

Requirements

Key technical and professional requirements. Education details are summarized separately under Education Requirements.

• Must-have: 6–14 years of digital verification experience with strong expertise in SystemVerilog, UVM methodology, and constrained-random verification.
• Must-have: Proficiency with verification tools and flows (simulators, waveform viewers, coverage tools, regression management).
• Must-have: Scripting experience for automation (Python, Perl, Tcl).
• Must-have: Solid understanding of computer architecture including memory hierarchies, bus protocols, and high-performance compute subsystems.
• Must-have: Experience debugging RTL and performing root-cause analysis; effective communication and ability to work in cross-functional, multicultural teams; English proficiency; availability for business travel.
• Nice-to-have: Experience with formal verification techniques and tools.
• Nice-to-have: Semiconductor product experience in automotive, industrial, or embedded systems.
• Nice-to-have: Experience using AI tools to accelerate code development, debugging, and verification productivity.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.