Senior Staff Engineer, Chip Implementation

Job Title

Senior Staff Engineer, Chip Implementation

Role Summary

Lead and execute RTL-to-gate synthesis, static timing analysis (STA), and timing closure for low-power, chiplet-based MCU designs on cost-optimized mature process nodes. Work within the chip implementation team and with cross-functional groups (RTL, physical design, DFT, verification, architecture, packaging) to meet power, performance, area, quality, and schedule targets.

Experience Level

Senior — corresponds to an experienced engineer. The role requires substantial industry experience (the posting specifies 10+ years).

Responsibilities

Primary implementation and methodology responsibilities:

• Drive and support RTL-to-gate synthesis flows for multi-die and chiplet-based MCU designs.
• Perform STA and lead timing closure across multiple modes, corners, and operating conditions to support sign-off.
• Optimize timing, power, and area within mature-node process constraints and product cost targets.
• Resolve complex implementation, timing, and sign-off issues with cross-functional teams.
• Develop and align full-chip and block-to-top constraints to achieve hierarchical timing convergence.
• Execute and improve synthesis, STA, ECO, and timing-closure methodologies and automation.
• Evaluate EDA tools, flows, and automation opportunities to improve quality of results and turnaround time.

Requirements

Core skills and experience required. Education details are summarized separately below.

• Extensive hands-on experience with mature-node technologies (examples: 22nm, 12nm) and low-power design techniques.
• Deep expertise with Synopsys/Cadence synthesis tools, STA tools, and implementation sign-off flows.
• Strong experience in multi-mode, multi-corner timing analysis, constraint development, and timing convergence.
• Proven experience driving timing closure for external interfaces (SPI, I2C, Ethernet, CAN, or similar).
• Experience with hierarchical timing closure and block-to-top constraint alignment for full-chip convergence.
• Expertise with UPF/CPF power intent, clock gating, multi-voltage domains, and power-aware implementation flows.
• Experience executing ECO flows for timing fixes and late-stage design changes.
• Strong scripting and automation skills (Tcl, Perl, Python) for synthesis/STA/reporting/regression efficiency.
• Effective communication, problem solving, and collaboration skills for global cross-functional teams.

Nice-to-have:

• Experience with timing sign-off for chiplet-based or multi-die designs.

Education Requirements

BTech or MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science is specified. The posting also indicates 10+ years of relevant ASIC/SoC implementation experience; equivalent practical experience may be considered based on the role. Certifications were not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.