Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Job Title

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Role Summary

Senior synthesis and front-end ASIC implementation engineer responsible for timing-constraint development, synthesis flows, ECOs, LEC, STA, UPF, and timing closure for complex SoC and block-level designs. Works across Architecture, RTL, DFT, Analog, and Physical teams to deliver designs in advanced technology nodes.

Experience Level

Senior-level. The role targets engineers with significant industry experience (typical expectation: 5+ years in ASIC implementation/synthesis). Candidates with a Master's or PhD and 3–5 years of relevant experience are also considered per the original posting.

Responsibilities

Core responsibilities include front-end implementation, timing, and synthesis activities for high-speed SoC designs.

• Develop and validate timing constraints and consolidated timing modes for synthesis, place-and-route, and chip timing sign-off.
• Perform logic synthesis and physical-aware synthesis for SOC and block-level designs.
• Execute and own flows such as UPF development, LEC/LEC checks, functional ECOs, and netlist handoff readiness.
• Collaborate with Architecture, RTL, DFT, Analog, and Physical teams to analyze timing complexities and allocate timing budgets.
• Analyze power/performance/area tradeoffs and translate targets into front-end implementation decisions.
• Debug tool issues and coordinate with EDA vendors to resolve or mitigate problems.
• Automate front-end flows and processes using scripting to improve repeatability and throughput.
• Document best practices and lessons learned to improve future project execution.

Requirements

Minimum and preferred technical qualifications (degree information summarized separately below).

• Minimum of 5 years industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII and timing closure methodology.
• Hands-on experience with synthesis and STA methodologies and tools.
• Proficiency in scripting for flow automation (Tcl, Python; Perl experience is a plus).
• Experience developing timing constraints for hierarchical designs and achieving timing closure.
• Experience performing functional ECOs and logical equivalence checks using industry-standard flows.
• Experience with UPF development and UPF validation tools.
• Familiarity with physical design and timing optimization techniques.
• Experience with advanced process nodes (e.g., TSMC N4/N5) and high-complexity silicon.
• Strong problem-solving skills, attention to detail, and effective cross-functional communication.

Nice-to-have: practical experience with Fusion Compiler (physical-aware synthesis), Conformal ECO/Conformal Low Power, experience at 5nm/4nm nodes, and prior vendor interaction for EDA issue resolution.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field is expected. A Master’s degree or PhD in these fields is acceptable and the posting indicates alternate experience thresholds when an advanced degree is held (Master’s/PhD with ~3–5 years). The posting also permits equivalent professional experience in lieu of a degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.