Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Job Title

Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Role Summary

Senior timing/STA engineer responsible for timing signoff, constraint development, ECOs, and power-related timing analysis for complex SoC and chiplet designs. The role works with architecture, RTL, DFT, analog, and physical design teams to define signoff methodologies and achieve deterministic timing closure on advanced nodes.

Experience Level

Senior-level. Typical candidates have a minimum of 5 years of industry ASIC timing/STA experience. Hiring guidance provided: Bachelor's +5–10 years or Master's/PhD +3–5 years.

Responsibilities

Key responsibilities include:

• Develop and validate timing constraints for complex hierarchical SoC and block designs.
• Run and own STA signoff flows (post-route checks, signoff margins, corners, derates) using industry tools.
• Create timing ECOs, perform timing budgeting, and drive timing closure for high-speed designs.
• Collaborate with Architecture, RTL, DFT, Analog, and Physical teams to consolidate timing modes and constraints for signoff.
• Automate STA processes and flows with scripting (Tcl, Python) and produce QoR dashboards and histograms.
• Investigate and resolve EDA tool issues, including working with tool vendors for fixes or workarounds.
• Document best practices and lessons learned to improve future projects.

Requirements

Must-have skills and experience:

• Minimum of 5 years industry experience in ASIC timing and STA.
• Hands-on experience with STA signoff methodologies and implementation; familiarity with PrimeTime or equivalent tools.
• Strong understanding of full ASIC design flows from RTL to GDSII and timing closure processes.
• Proficiency in scripting to automate STA flows (Tcl, Python; Perl experience is useful).
• Experience with high-complexity silicon on advanced nodes (preferably TSMC N4/N5).
• Expertise in timing constraint development for hierarchical designs, timing ECO creation, and final signoff.
• Familiarity with physical design impacts and timing optimization strategies to meet performance, power, and area goals.
• Strong problem-solving, attention to detail, and effective cross-functional communication skills.

Education Requirements

Listing specifies a Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of related professional experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with 3–5 years of experience. Related technical fields and equivalent professional experience are accepted per the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.