Senior Staff Engineer, ASIC Chief Architect

Job Title

Senior Staff Engineer, ASIC Chief Architect

Role Summary

Lead definition and execution of system-level architecture for next-generation ASICs/SoCs across compute, memory, networking, security, and acceleration. Work with product management, silicon engineering, verification, firmware, and software teams to drive architectural tradeoffs from concept through production.

Provide technical leadership and mentorship to architecture teams; own technology roadmaps, PPA strategy, system modeling, and hardware/software co-design.

Experience Level

Senior-level. The role expects extensive experience in semiconductor/ASIC/SoC/processor architecture (guideline: 12+ years). Minimum experience requirements vary by degree—see Education Requirements.

Responsibilities

Primary responsibilities include:

• Define end-to-end architecture of complex ASIC/SoC products from concept to production.
• Lead system architecture across compute, memory, networking, security, and accelerators.
• Drive architectural decisions for DSP, CPU, GPU, AI/ML acceleration, packet processing, memory hierarchy, NoC, and chiplet architectures.
• Develop PPA (performance, power, area) and cost optimization strategies.
• Perform workload analysis, architectural modeling, performance simulation, and capacity planning.
• Drive hardware/software co-design and system partitioning decisions.
• Collaborate with design, verification, physical design, firmware, and software teams during silicon bring-up.
• Define technology roadmaps and mentor architecture teams; act as a top technical authority on system architecture.

Requirements

Must-have skills and experience:

• Extensive experience in semiconductor, ASIC, SoC, or processor architecture with a proven track record delivering complex silicon from concept to production (guideline: 12+ years).
• Deep technical expertise in DSP architectures, CPU and GPU architectures, hardware accelerators, and heterogeneous computing.
• Strong knowledge of memory subsystems, cache architectures, and memory controllers.
• Experience with packet processing, network processors, switching, routing, and traffic management.
• Familiarity with high-speed interfaces such as PCIe, Ethernet, CXL, and UCIe.
• Knowledge of NoC and chiplet architectures, power management, and PPA optimization.
• Experience in system modeling, architectural simulation, performance analysis, workload characterization, and HW/SW co-optimization.
• Experience with ASIC design flows and silicon bring-up; demonstrated leadership and mentoring of senior engineers and architects.

Nice-to-have:

• Experience with wireless communications, modem, networking, AI, or datacenter silicon.
• Track record of delivering high-volume commercial ASICs, patents, or industry-recognized technical contributions.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is listed as required in preferred/required qualifications; minimum qualifications accept a Bachelor's with additional experience. The posting specifies degree-plus-experience options: Bachelor's +6 years; Master's +5 years; PhD +4 years. Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.