Senior Staff Digital Design Engineer

Job Title

Senior Staff Digital Design Engineer

Role Summary

Lead micro-architecture and front-end digital design for power-management and analog-intensive ASICs from specification through silicon. Work with cross-functional teams (design, verification, P&R, test) to deliver optimized, low-power digital blocks and ensure design-to-silicon correlation.

Experience Level

Senior-level. The posting does not specify years of experience.

Responsibilities

Key responsibilities include end-to-end digital design ownership, verification, and silicon bring-up for power-management ICs.

• Define micro-architecture and digital/analog boundaries for PMICs and analog-intensive ICs.
• Design, implement and optimize digital functional blocks and RTL for low-power operation.
• Handle Clock Domain Crossing (CDC) across multiple domains ensuring glitch-free operation.
• Lead or collaborate on logic synthesis, static timing analysis (STA), formal verification and power estimation.
• Design controllers and data paths for OTP, MTP, eFuse, register read/write and analog trimming functions.
• Plan verification tests, develop test cases, and support pre- and post-silicon validation including silicon debug and root-cause analysis.
• Interface with place-and-route teams for digital hand-off and post-layout verification; support DFT strategy and integration.
• Evaluate silicon device area and power where required and produce high-quality documentation for owned blocks.

Requirements

Must-have technical skills and practical experience; optional items noted.

• Must-have: Hands-on RTL design and coding in Verilog/SystemVerilog.
• Must-have: Experience in logic design, micro-architecture, synthesis and timing analysis for complex digital circuits, ideally in power products/PMICs.
• Must-have: Proven experience with CDC handling, STA, and preparing timing constraints for block and top-level sign-off.
• Must-have: Experience with silicon bring-up, multiple silicon debugs and design-to-silicon correlation.
• Must-have: Ability to work independently and drive deliverables on schedule; clear technical communication across multi-site teams.
• Nice-to-have: Experience with OTP/MTP/eFuse controllers, analog trimming flows, DFT architecture and integration.
• Nice-to-have: Familiarity with power-chip interfaces and protocols (e.g., I2C, PMBus) and formal verification techniques.

Education Requirements

Degree-level qualification in Electronics Engineering (the posting specifies a degree in Electronics Engineering). No additional degrees, fields, certifications, or equivalent-experience language were provided.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.