Senior Staff Digital Design Engineer

Job Title

Senior Staff Digital Design Engineer

Role Summary

As a Senior Staff Digital ASIC Design Engineer in the DCE - Connectivity Business Group you will design and deliver high-performance connectivity silicon for AI-scale data centers. The role focuses on micro-architecture, RTL development, DSP-driven datapaths, and cross-functional integration from specification through tape-out and post-silicon bring-up.

Experience Level

Senior-level. 3–10+ years of industry experience; the posting cites typical ranges of 5–10+ years with a Bachelor's degree or 3–5+ years with a Master's/PhD.

Responsibilities

Accountable for block-level architecture, RTL delivery, front-end flow ownership, verification planning, and integration into larger SoC assemblies.

• Collaborate with systems and architecture teams to define SoC-level performance, power, area, and feature requirements.
• Translate product and protocol requirements into detailed micro-architecture for subsystems, datapaths, and DSP pipelines.
• Develop and deliver synthesizable SystemVerilog RTL for assigned blocks.
• Own front-end design flow tasks: lint, CDC/RDC, synthesis, timing constraints, and DFT readiness.
• Partner with STA and P&R teams to support timing closure, floorplanning, congestion analysis, and optimizations.
• Integrate digital logic into larger subsystems and ensure clean, reusable interfaces.
• Design parameterized, maintainable datapaths and DSP building blocks.
• Define verification strategies with DV teams and support pre-silicon validation (emulation, FPGA prototyping).
• Lead post-silicon bring-up and debugging with lab and systems teams to validate performance and resolve complex issues.
• Participate in design and micro-architecture reviews and mentor junior engineers.

Requirements

Core technical skills and proven experience delivering large-scale ASIC designs. Preferred skills are listed inline as "Nice to have." Education details are in the Education Requirements section below.

• Must have: Extensive experience in digital ASIC micro-architecture and RTL implementation (SystemVerilog preferred).
• Must have: Strong background in high-performance DSP and high-speed datapath design (pipelined arithmetic units, packet processing, memory subsystems, control/state machines).
• Must have: Proficiency with front-end design flows including lint, CDC/RDC, synthesis, STA, and power/performance optimization.
• Must have: Familiarity with Ethernet protocols and networking standards (MAC, PCS framing, flow control).
• Must have: Demonstrated ability to collaborate across architecture, verification, physical design, firmware, and systems teams to achieve tape-out quality designs.
• Must have: Strong debug skills across RTL simulation, emulation, FPGA prototypes, and silicon bring-up.
• Must have: Experience with advanced process nodes (e.g., 5nm, 3nm) and their impact on timing, power, and signal integrity.
• Nice to have: Experience with FEC architectures (LDPC, RS, BCH) and PHY-level DSP pipelines, equalization, and clock recovery.
• Nice to have: Advanced DSP algorithm implementation experience (adaptive equalization, channel estimation, high-throughput filtering).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. PhD is a plus.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.