Senior/Staff DFT Engineer
Axelera AIJob Title
Senior/Staff DFT Engineer
Role Summary
Join the multicore in-memory-compute SoC team to design, implement, and validate design-for-test (DFT) solutions for complex SoCs. Collaborate with RTL, verification, and physical design engineers across Europe to improve silicon testability, coverage, and yield.
Experience Level
Senior level — typically 5+ years of DFT engineering experience on complex SoC projects.
Responsibilities
Main responsibilities include implementing and supporting DFT flows and silicon bring-up:
- Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
- Integrate DFT solutions with RTL, verification, and physical design teams.
- Support silicon bring-up, debug test failures, and help optimize test coverage and yield.
- Contribute to DFT methodology improvements and share best practices with the team.
Requirements
Must-have technical skills and experience:
- Minimum 5 years of DFT engineering experience on complex SoC projects.
- Experience with SystemVerilog RTL, TCL, Python, and Unix/Linux workflows.
- Core knowledge of hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification.
- Experience with Siemens, Synopsys, or Cadence DFT toolchains.
- Strong problem-solving and collaboration skills for cross-discipline debugging.
Nice-to-have:
- Familiarity with IEEE 1149.x/1500/1687 standards, synthesis flow, and timing analysis.
Education Requirements
Not specified.
About the Company
Company: Axelera AI
Headquarters: Eindhoven, Netherlands
Deep-tech startup developing a next-generation AI platform (Metis™) and AI accelerators/in-memory compute SoCs. The company has raised $120M, employs around 220 people across multiple countries, and operates European offices while focusing on high-performance AI hardware and software.
