Senior Staff Design Verification Engineer — Memory Sub-System (DDR/LPDDR/HBM)

Job Title

Senior Staff Design Verification Engineer — Memory Sub-System (DDR/LPDDR/HBM)

Role Summary

Work in the Center of Excellence within Marvell's Custom Compute and Storage business unit to design and verify high-speed memory IP subsystems used in SoCs for data center, cloud, and AI applications.

Responsible for creating verification plans, building UVM/SystemVerilog environments, executing protocol- and performance-level verification for DDR/LPDDR/HBM interfaces, and collaborating with design, architecture, firmware, and validation teams to deliver production-ready IP.

Experience Level

Senior (Senior Staff). 5–10 years of experience in ASIC/SoC verification as indicated in the posting.

Responsibilities

Primary responsibilities include verification planning, environment and test development, debugging, and cross-team collaboration to ensure IP quality and compliance.

• Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3).
• Build and enhance UVM/SystemVerilog verification environments.
• Develop testbenches, sequences, and checkers for functional and performance validation.
• Perform protocol-level verification for memory controllers and PHY interfaces.
• Analyze and debug simulation failures, identify root causes, and drive resolutions.
• Work closely with design, architecture, and firmware teams to ensure coverage closure and specification compliance.
• Contribute to coverage-driven verification (functional, code, and assertion coverage).
• Support emulation/FPGA validation and post-silicon bring-up when required.
• Review design specifications and provide feedback for testability and robustness.

Requirements

Key requirements — must-have and nice-to-have skills.

• Must-have: 5–10 years of ASIC/SoC verification experience focused on memory interfaces.
• Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
• Expertise in SystemVerilog and UVM methodology.
• Experience debugging complex verification issues and using industry-standard simulation, waveform, and coverage tools.
• Solid understanding of digital design fundamentals.

Nice-to-have:

• Knowledge of JEDEC standards for DDR/LPDDR/HBM.
• Experience with assertion-based verification (SVA).
• Exposure to performance modeling and traffic generation.
• Experience with emulation platforms (e.g., Palladium, Veloce).
• Scripting skills (Python, Perl, Shell).
• Experience with low-power verification (UPF) and post-silicon bring-up.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.