Senior Staff Design Verification Engineer – Memory Sub-System
Marvell TechnologyJob Title
Senior Staff Design Verification Engineer – Memory Sub-System
Role Summary
Join the Center of Excellence within Marvell's Custom Compute and Storage Business Unit to design and verify IP subsystems for high-speed memory interfaces used in data center, cloud, and AI SoCs. The role focuses on developing verification environments and executing verification plans to ensure protocol compliance, performance, and first-pass silicon success.
The position works closely with architecture, RTL design, firmware, and silicon validation teams to deliver reusable, production-ready memory controller and PHY verification components.
Experience Level
Senior-level. The posting requests approximately 5–10 years of ASIC/SoC verification experience.
Responsibilities
Primary verification and validation responsibilities for memory subsystems and associated IP.
- Develop and execute verification plans for DDR4/DDR5, LPDDR4/LPDDR5, and HBM2/HBM3 interfaces.
- Build and maintain UVM/SystemVerilog verification environments, testbenches, sequences, and checkers.
- Perform protocol-level verification for memory controllers and PHY interfaces and drive coverage closure.
- Analyze simulation failures, identify root causes, and coordinate fixes with design and firmware teams.
- Contribute to coverage-driven verification including functional, code, and assertion coverage.
- Support emulation/FPGA validation and post-silicon bring-up (preferred).
- Review design specifications and provide feedback on testability and robustness.
Requirements
Must-have skills and experience; preferred items noted separately.
- Must-have: 5–10 years of ASIC/SoC verification experience focused on memory subsystems.
- Must-have: Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
- Must-have: Expertise in SystemVerilog and UVM methodology.
- Must-have: Experience debugging complex verification issues and using industry-standard simulation, waveform, and coverage tools.
- Must-have: Solid understanding of digital design fundamentals.
- Nice-to-have: Knowledge of JEDEC standards for DDR/LPDDR/HBM and assertion-based verification (SVA).
- Nice-to-have: Experience with performance modeling/traffic generation, emulation platforms (e.g., Palladium, Veloce), scripting (Python/Perl/Shell), and low-power verification (UPF/CPF).
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is specified.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
