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Senior / Staff Design Verification Engineer

SiFive
May 20, 2026
Full-time
On-site
Ahmedabad, Gujarat, India
Verification Jobs, Level - Senior

Job Title

Senior / Staff Design Verification Engineer

Role Summary

Join SiFive's silicon engineering team to own verification activities for complex SoCs and IP blocks. The role covers testplan definition, verification environment development, debugging, coverage analysis, and verification sign-off.

This role requires delivering tape-out–ready verification solutions and mentoring junior engineers.

Experience Level

Senior-level — 5+ years of ASIC/SoC design verification experience.

Responsibilities

The engineer will lead verification planning, environment and test development, debugging, and closure.

  • Author and own feature-driven verification testplans based on architectural and micro-architectural specs.
  • Design, implement, and maintain constrained-random SystemVerilog/UVM verification environments and testbenches.
  • Define verification strategies at block, sub-system, and SoC levels, using simulation and formal techniques where appropriate.
  • Debug complex test failures, identify RTL or testbench root causes, and collaborate with Design and Architecture teams to resolve issues.
  • Define and implement functional and code coverage models; drive coverage closure to sign-off targets.
  • Provide technical mentorship, perform code and testplan reviews, and raise engineering standards across the team.

Requirements

Must-have technical skills and experience for the role.

  • Strong digital design and computer architecture fundamentals (FIFO, pipelines, memory controllers, clock/reset domains).
  • Advanced proficiency in SystemVerilog and Object-Oriented Programming concepts.
  • Extensive hands-on UVM experience (sequences, drivers, monitors, scoreboards, predictors).
  • Proven experience writing complex functional coverage and closing both functional and code coverage.
  • Proven debugging skills with industry tools (e.g., Verdi, DVE) and systematic root-cause methodology.
  • Familiarity with standard on-chip protocols such as AXI, AHB, APB, PCIe, NVMe, USB, or Ethernet (depending on team focus).
  • Scripting and automation experience (Python, Perl, Tcl) and Shell scripting to support verification workflows.
  • Strong analytical, communication, and cross-functional collaboration skills; self-motivated and detail-oriented.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related fields such as ECE, EEE, Embedded Systems, or VLSI.


About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.

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Date Posted: 2026-05-19