Senior Staff Design Verification Engineer
RenesasJob Title
Senior Staff Design Verification Engineer
Role Summary
Provide technical leadership for verification of advanced memory-interface products used in data center, AI, and cloud computing applications, with emphasis on next-generation DDR memory data buffer designs.
Work with design teams to define verification strategy, develop SystemVerilog/UVM environments, execute verification campaigns, and drive coverage closure.
Experience Level
Senior - 10+ years of semiconductor design verification experience.
Responsibilities
Lead verification strategy and execution for complex block- and system-level designs; mentor engineers and coordinate cross-team verification efforts.
- Define verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
- Develop, optimize, and maintain SystemVerilog/UVM verification environments and testbenches.
- Drive verification execution, functional coverage collection, debugging, and coverage closure.
- Own significant verification efforts and make independent technical decisions on methods and priorities.
- Analyze complex verification and design issues, determine root causes, and implement solutions.
- Collaborate with design engineers and stakeholders to ensure designs meet functional and performance requirements and are verifiable.
- Develop reusable verification solutions, methodologies, and best practices for broader use.
- Provide technical leadership during architecture, feasibility, and design reviews.
- Mentor and provide technical guidance to verification engineers across projects and experience levels.
- Communicate verification status, technical risks, and readiness to engineering leadership and project stakeholders.
Requirements
Must-have skills and experience; preferred items noted separately.
- 10+ years of related experience in semiconductor design verification with technical leadership of complex verification efforts.
- Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM.
- Experience defining verification strategies and developing verification plans from product and design specifications.
- Strong experience in functional verification, coverage, checkers, test development, debugging, and coverage closure.
- Demonstrated ability to independently resolve complex technical problems and make verification methodology decisions.
- Proven experience mentoring and providing technical guidance to other engineers.
- Nice-to-have: experience with DDR4/DDR5 or other memory interfaces, data buffers, high-speed memory technologies, and leading verification across multiple blocks or teams.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
