Senior Staff Design Verification Engineer

Job Title

Senior Staff Design Verification Engineer

Role Summary

Senior staff engineer responsible for driving SoC/ASIC verification efforts for a programmable in-memory computing architecture. Work with architects, RTL designers, and validation teams to define verification strategy, build verification environments, execute tests, and debug silicon bring-up.

Hybrid role based at the Santa Clara headquarters (onsite approximately 3 days per week).

Experience Level

Senior-level. The posting expects extensive industry experience (see Education Requirements for specific years-of-experience guidance tied to degree level).

Responsibilities

Core responsibilities include leading verification activities across the SoC lifecycle and delivering robust verification environments and debug capabilities.

• Lead SoC verification from architecture through tape-out and bring-up.
• Define and implement verification strategy and test plans for complex IP and SoC blocks.
• Develop and maintain UVM/OVM-based verification environments and testbenches.
• Create constrained-random tests, coverage models, and assertions using SystemVerilog.
• Debug functional failures at RTL and system levels; collaborate with design and firmware teams to isolate issues.
• Drive automation, regression infrastructure, and verification flow improvements.
• Mentor and guide junior engineers and contribute to cross-functional coordination for tape-out cycles.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Extensive hands-on experience with SystemVerilog-based verification, including randomization, coverage, and assertions.
• Proven experience with UVM/OVM/VMM methodologies and building verification environments.
• Practical experience in ASIC/SoC verification tests and debug across pre- and post-silicon stages.
• Experience with full SoC verification cycle: planning, execution, and issue resolution toward tape-out.
• Strong problem-solving skills and ability to operate in a fast-paced startup environment focused on AI workloads.

Nice-to-have / preferred:

• Experience with C/C++ and SystemC.
• Track record of leading creation and implementation of multiple SoC verification environments and successful tape-out efforts.

Education Requirements

BS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience; or MS in Electrical Engineering, Computer Science, or related field preferred with 7+ years industry experience. Fields specified: Electrical Engineering and Computer Science (related technical fields acceptable).

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.