Senior Staff Design Verification Engineer

Job Title

Senior Staff Design Verification Engineer

Role Summary

The Senior Staff Design Verification Engineer is a senior technical contributor within the Smart Analog and Sensors verification organization, responsible for verification planning, methodology, testbench architecture, functional validation, coverage closure, and debug for complex SoC and subsystem designs.

The role collaborates with architecture, RTL, design, and system teams to ensure silicon quality and drive verification reuse and productivity across programs.

Experience Level

Senior-level. Minimum 8 years of industry experience in digital or SoC design verification.

Responsibilities

Provide technical leadership and deliver verification solutions for complex subsystems and full-chip designs.

• Develop and maintain advanced UVM/SystemVerilog verification environments for subsystem and SoC verification.
• Define verification plans from architecture and design specifications and drive coverage closure.
• Create reusable verification infrastructure: agents, scoreboards, monitors, checkers, and coverage models.
• Develop constrained-random and directed tests to validate functional and corner-case behavior.
• Implement protocol checkers, assertions, stimulus generation, and automation for regressions and reporting.
• Analyze code/functional/assertion coverage and debug RTL, testbench, integration, and simulation failures.
• Promote verification reuse and best practices across programs and improve verification productivity.
• Mentor junior verification engineers and contribute to methodology improvements.
• Participate in cross-functional reviews and collaborate globally to meet project milestones.

Requirements

Must-have technical skills, experience, and working behaviors for success in this role.

• Minimum 8 years industry experience in digital or SoC verification.
• Strong expertise in SystemVerilog and UVM-based verification methodologies.
• Experience developing complex verification environments for subsystem and full-chip verification.
• Hands-on experience with constrained-random verification, assertions (SVA), coverage-driven verification, and debug workflows.
• Experience verifying processors, memory subsystems, interconnects, and complex SoC architectures.
• Solid understanding of RTL design concepts and simulation/debug methodologies using industry-standard simulators and verification tools.
• Proficiency in scripting for automation (Python, Perl, Tcl, or Shell).
• Strong analytical, problem-solving, communication skills, and ability to work in a global, multicultural environment.
• Willingness to travel up to 10% for project collaboration.
• Nice-to-have: experience with verification automation/CI-CD, emulation/FPGA prototyping, formal verification, and low-power verification techniques.
• Nice-to-have: familiarity with ARM-based SoC architectures and bus protocols (AXI, AHB, APB, PCIe, Ethernet).

Education Requirements

Required: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, or a related discipline. Preferred: Master's degree or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.