Senior Staff Design Verification Engineer

Job Title

Senior Staff Design Verification Engineer

Role Summary

Senior verification engineer responsible for end-to-end functional verification of mixed-signal ASICs at block and chip level. The role partners with digital and analog design, firmware/software, systems, and manufacturing test teams to deliver high-quality silicon.

Work covers UVM-based testbenches, formal methods, emulation/acceleration, gate-level simulation, and software-driven verification in a collaborative engineering environment.

Experience Level

Senior-level. Typical experience guidance: Bachelor’s with 10+ years, Master’s with 8+ years, PhD with 6+ years of relevant industry experience in silicon design or ASIC verification.

Responsibilities

Primary responsibilities include planning, executing, and improving verification for mixed-signal ASICs.

• Develop verification plans aligned to design and system requirements.
• Perform functional verification at block and chip level, including pre-silicon and post-silicon activities.
• Design and implement UVM-based testbenches, infrastructure, scoreboards, checkers, and assertions.
• Create directed and constrained-random test suites and drive coverage closure.
• Run and debug gate-level simulations and address timing/back-annotation issues.
• Perform failure analysis, regression triage, and debug functional and timing-related issues.
• Develop and maintain digital and mixed-signal behavioral models to support verification.
• Support verification flow, automation, regressions, and infrastructure development.
• Collaborate cross-functionally with design, systems, firmware/software, and manufacturing test teams.

Requirements

Must-have technical skills and experience for successful execution of the role.

• Significant industry experience in silicon design and/or ASIC verification.
• Proficiency with HDLs: Verilog and/or VHDL.
• Proficiency with HVLs: SystemVerilog and UVM (or OVM/AVM/Vera).
• Solid understanding of digital design principles and system architecture.
• Experience with testbench architecture, stimulus generation, regression execution, and debug.
• Experience with coverage analysis and coverage-driven verification.
• Ability to work effectively in cross-disciplinary, team-oriented environments.

Education Requirements

Requires a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Experience guidance provided: Bachelor's +10 years, Master's +8 years, PhD +6 years of relevant industry experience in silicon design and/or ASIC verification.

About the Company

Company: Cirrus Logic

Headquarters: Austin, TX, United States

Designer and manufacturer of high-precision analog and mixed-signal integrated circuits, specializing in audio and voice processing solutions for consumer electronics and mobile devices, including audio codecs, converters, and SoCs.