Senior / Staff Design Verification Engineer

Job Title

Senior / Staff Design Verification Engineer

Role Summary

Senior/Staff Design Verification Engineer responsible for owning the verification lifecycle of complex SoCs and IP — from testplan and environment architecture to debug and coverage closure.

Work with Design, Architecture and Validation teams to deliver tape-out–ready hardware and verification environments.

Experience Level

Senior-level — typically 5+ years of ASIC/SoC design verification experience.

Responsibilities

Primary responsibilities include planning, implementing and closing verification for blocks, subsystems or SoCs.

• Define and author feature-driven verification testplans based on architectural and micro-architectural specifications.
• Design, build, and maintain scalable, reusable constrained-random verification environments using SystemVerilog and UVM.
• Define verification strategies across block, sub-system and SoC levels, incorporating simulation and formal methods where applicable.
• Debug complex test failures, identify RTL or testbench defects, and collaborate with designers and architects to resolve issues.
• Implement and analyze functional (covergroups, coverpoints, crosses) and code coverage; drive verification to coverage closure.
• Mentor and provide technical guidance to junior verification engineers; participate in code and testplan reviews.

Requirements

Key technical and professional must-have skills. Education expectations are listed under Education Requirements below.

• 5+ years of dedicated ASIC/SoC design verification experience.
• Advanced proficiency in SystemVerilog and object-oriented concepts.
• Extensive, hands-on experience with UVM (writing sequences, drivers, monitors, scoreboards, predictors).
• Strong digital design fundamentals: pipelines, FIFOs, memory controllers, clock/reset domains.
• Proven experience writing complex functional coverage and closing both functional and code coverage.
• Proficiency with industry-standard debug tools (e.g., Verdi, DVE) and systematic root-cause debugging practices.
• Scripting skills for verification automation (Python, Perl or Tcl) and shell scripting.
• Strong analytical, communication, and collaboration skills; ability to mentor teammates.

Nice-to-have:

• Familiarity with on-chip protocols (AXI, AHB, APB, PCIe, NVMe, USB, Ethernet) depending on team focus.
• Experience applying formal verification techniques.

Education Requirements

Bachelor's or Master's degree in Electrical & Computer Engineering (ECE), Electrical Engineering (EEE), Embedded Systems, VLSI as stated in the posting.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.