Senior Staff Design Engineer - Memory Subsystem COE

Job Title

Senior Staff Design Engineer - Memory Subsystem COE

Role Summary

The Senior Staff Design Engineer will define, design, implement, and integrate DDR/LPDDR/HBM memory subsystem IP for Marvell SoCs within the Center of Excellence (COE). The role coordinates with architecture, verification, physical design, firmware, and validation teams to deliver production-ready, reusable RTL subsystems.

The position focuses on subsystem micro-architecture, RTL development, integration, silicon bring-up support, and improving design quality and reuse across projects.

Experience Level

Senior — typically 8–10+ years of relevant RTL design experience, working at subsystem and SoC integration levels.

Responsibilities

Key responsibilities include:

• Define micro-architecture and deliver RTL for DDR/LPDDR/HBM controllers and memory subsystems.
• Translate architecture requirements into robust RTL implementations and interfaces.
• Collaborate with design verification on test plans, debugging, and coverage closure.
• Work with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug in partnership with firmware and validation teams.
• Drive coding best practices, design quality improvements, and RTL reuse across projects.
• Participate in design and milestone reviews and lead cross-functional technical discussions.
• Mentor and provide technical leadership to junior designers in the DDR/HBM domain.

Requirements

Must-have technical skills and experience:

• Proven experience delivering complex DDR, LPDDR, or HBM controllers or subsystems from architecture through RTL closure.
• Strong hands-on RTL development using SystemVerilog/Verilog.
• Familiarity with DDR/HBM JEDEC specifications.
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Solid understanding of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience with lint, CDC/RDC analysis, synthesis, and design sign-off flows.
• Experience using industry-standard EDA tools (Synopsys, Cadence, Mentor/Siemens).
• Proficiency in scripting languages (TCL, Perl, Python) and version control systems (GIT, SVN).

Nice-to-have:

• End-to-end DDR/HBM subsystem RTL design execution and sign-off experience.
• Experience designing high-performance, low-latency datapaths and handling ordering, coherency, and error mechanisms.
• Proven ability to debug functional and performance issues at subsystem and SoC levels.
• Familiarity with post-silicon bring-up and debug methodologies.
• Prior mentoring and cross-functional technical leadership experience.

Education Requirements

Master's or Bachelor's degree in Electronics or Electrical Engineering is required per the posting. The role expects approximately 8–10+ years of relevant RTL design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.