Senior Staff Collateral Design and DFM Engineer
Intel CorporationJob Title
Senior Staff Collateral Design and DFM Engineer
Role Summary
Join Intel Foundry's Manufacturing Development Customer Engineering (MDCE) team to develop and scale Design for Manufacturability (DFM) methodologies for advanced logic nodes and high-volume manufacturing. The role interfaces across Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to improve yield, performance, and ramp speed for foundry customers.
Primary site is Santa Clara, CA with additional locations in Phoenix, AZ and Hillsboro, OR. The position uses a hybrid work model.
Experience Level
Senior — requires approximately 6+ years of relevant industry experience (DTCO/DFM in a foundry or advanced technology development environment).
Responsibilities
Provide technical leadership to define, validate, and evolve DFM and collateral design rules, tools, and flows that enable manufacturing readiness and yield improvement.
- Lead cross-functional teams to define and refine DFM rules and mitigation strategies for advanced nodes.
- Translate silicon learning and yield analytics into actionable feedback for design teams and flows.
- Develop and optimize yield tools and flows to support inline yield detection and continuous process improvement.
- Define DFM methodologies by predicting layout/design marginalities and creating robust mitigation measures.
- Drive scribe line layout design and process monitoring structures for characterization and manufacturing readiness.
- Manage design-rule development, validation, and waiver processes to align manufacturing constraints with customer requirements.
- Serve as the technical interface among Process Integration, Yield, Device, and Design stakeholders.
- Develop tailored DFM solutions to support diverse foundry customers and market segments.
Requirements
Key technical and professional requirements. Degrees and academic expectations are listed under Education Requirements below.
- Must-have: 6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
- Experience with DTCO methodologies, including SRAM and standard cell design.
- Proven experience leading cross-functional teams to define derivative architectures, design rules, transistor and interconnect considerations.
- Hands-on experience with advanced-node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD).
- Nice-to-have: Scripting/coding for design automation and flow development; experience with physical design flows for yield analysis, DRC, and verification.
- Experience in a foundry environment delivering DFM solutions to varied customer requirements is a plus.
Education Requirements
Minimum: Master’s degree in Electrical Engineering, Physics, or a closely related field (or equivalent combination of industry experience, internships, coursework, or research). Preferred: Ph.D. in Electrical Engineering, Physics, or a closely related field. No specific certifications were listed.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
