Senior Staff Applications Engineer

Job Title

Senior Staff Applications Engineer

Role Summary

Technical customer-facing engineer in the Customer Success Group focused on ASIC physical design. You will support pre-sales and post-sales engagements, debug advanced RTL-to-GDSII issues, develop practical methodologies, and work with product teams to improve Synopsys tools.

This role is based in Sunnyvale, CA and involves hands-on technical work with customer design teams to enable successful tape-outs at advanced process nodes.

Experience Level

Senior level - typical experience: Bachelor's degree +9 years ASIC physical design experience, or Master's degree +7 years (see Education Requirements for details).

Responsibilities

Primary responsibilities include customer technical support, methodology development, and collaboration with product teams.

• Support pre-sales and post-sales technical engagements and live demonstrations of Synopsys physical design tools.
• Debug complex physical design problems across placement, routing, timing closure, and congestion in advanced nodes.
• Develop and document technical methodologies for clock tree synthesis, optimization, macro placement, and timing closure.
• Build proof-of-concept designs and benchmarks showing PPA improvements versus customer baselines.
• Translate customer issues into product feature requests and methodology improvements with product engineering teams.
• Train and mentor customer engineers on advanced tool capabilities and flows.
• Travel onsite to customer facilities for critical engagements and tape-out support (up to ~30%).

Requirements

Must-have technical skills and domain experience.

• Extensive hands-on ASIC physical design experience with RTL-to-GDSII flows, including placement, optimization, CTS, and routing.
• Proficiency with Synopsys backend tools such as Fusion Compiler, ICC2, Design Compiler, and PrimeTime.
• Practical experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoCs.
• Deep understanding of advanced-node design challenges (FinFET behavior, multi-patterning, electromigration) and production tape-out practices.
• Ability to create benchmarks and POC designs to quantify PPA improvements and justify methodology changes.
• Strong customer-facing skills: debug on-site, communicate technical tradeoffs to engineers and managers, and operate under tape-out pressure.
• Willingness and ability to travel to customer sites for hands-on support (up to 30%).

Nice-to-have:

• Experience with H-Tree and multi-source clock tree synthesis methodologies.
• History of influencing product roadmaps or publishing customer success stories, white papers, or conference presentations.

Education Requirements

Bachelor's degree in Electrical Engineering (or equivalent) with 9+ years of relevant ASIC physical design experience, or Master's degree with 7+ years. Equivalent practical experience is explicitly accepted.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.