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Senior Staff Analog Circuit Design Engineer - SerDes

Intel Corporation
May 17, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$164,470 - $361,480 USD yearly
Semiconductor IP Jobs, Level - Senior

Job Title

Senior Staff Analog Circuit Design Engineer - SerDes

Role Summary

Design, implement, and validate analog and mixed-signal circuits for high-speed SerDes transceivers (112G and 224G). Work within a SerDes engineering team, collaborating with system architects, digital designers, layout engineers and validation teams to deliver high-performance analog blocks and subsystems.

Work includes pre- and post-silicon design, verification, performance optimization, and mentoring junior analog designers.

Experience Level

Senior-level (Senior Staff). The posting lists a minimum of 2+ years of analog/mixed-signal design experience; candidates are expected to have substantial hands-on experience in high-speed SerDes or equivalent applications.

Responsibilities

Core responsibilities focus on analog block design, verification, and cross-functional collaboration.

  • Design and implement advanced analog and mixed-signal circuits for 112G and 224G SerDes.
  • Define, verify, and optimize high-performance analog blocks and subsystems (PLL, CDR, CTLE, DFE, ADC, LDO, reference generation, transmitter/receiver).
  • Participate in technical design reviews and cross-disciplinary discussions with system architects and digital/layout teams.
  • Perform post-silicon validation, debugging, and performance tuning.
  • Provide guidance to layout engineers and mentor junior analog designers.
  • Develop and document designs, simulation results, and test plans.

Requirements

Must-have technical skills and experience; preferred items listed separately.

  • 2+ years of analog/mixed-signal circuit design experience for high-speed SerDes or similar applications (as listed by the employer).
  • Hands-on experience with analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
  • Experience with advanced FinFET CMOS process technologies.
  • Domain experience in one or more of: PLL, CDR, CTLE, DFE, ADC, LDO, reference generation, or transmitter design.
  • Strong analog fundamentals: noise, linearity, matching, and stability analysis; hands-on debugging skills.
  • Good communication, documentation skills, and ability to work in cross-functional teams.

Nice-to-have:

  • Experience with transmitter/receiver design, CDR loops, equalization techniques, and signal integrity/channel modeling.
  • Familiarity with next-generation high-speed standards (e.g., PCIe 6.0, 800G Ethernet, JESD) and prior work on PCIe/Gen4/Gen5 or Ethernet (100G/400G).
  • Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (Python, Tcl).

Education Requirements

Minimum: Bachelor’s degree in Electrical Engineering, Electronics Engineering or a STEM-related field (or equivalent practical experience as noted by the employer). Preferred: Ph.D. in Electrical Engineering, Electronics Engineering or related STEM field. The posting indicates degree attainment may be satisfied via a combination of industry experience, internships, coursework, or research.


About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

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Date Posted: 2026-05-15