Senior Staff AMS Design Verification Engineer

Job Title

Senior Staff AMS Design Verification Engineer

Role Summary

Lead a team responsible for analog and mixed-signal (AMS) design verification to ensure specification compliance and first-pass silicon success. Drive verification strategy, develop reusable verification environments, and coordinate across analog, digital, systems, test, and validation teams.

Experience Level

Senior-level. The role expects significant experience; the posting indicates 10+ years in advanced verification methodologies and ownership of complex digital and mixed-signal verification.

Responsibilities

Accountable for planning, delivering, and improving AMS verification for complex ICs and subsystems, and for technical leadership of the verification team.

• Lead analog & mixed-signal verification efforts to meet performance, power, and schedule targets.
• Define and deploy verification strategy and methodologies for mixed-signal IPs, including UVM-based verification IP.
• Develop and maintain verification plans, tests, coverage, checkers, and reusable testbench structures.
• Provide technical interface to contract DV resources and cross-functional teams; participate in design and review meetings.
• Debug RTL for design intent and interface with analog/digital designers and systems engineers.
• Mentor and develop verification engineers; delegate tasks and enforce methodology and analog best practices.
• Represent analog verification in management and customer reviews and drive cross-site initiatives & process improvements.
• Perform other reasonable tasks as assigned by management.

Requirements

Key technical and leadership requirements. Education details are summarized separately under Education Requirements.

• 10+ years' hands-on experience in advanced verification methodologies and owning verification of complex mixed-signal designs.
• Strong fundamentals in analog and mixed-signal circuit concepts and topologies.
• Experience with mixed-signal verification environments and simulation/regression tools (examples: Cadence Virtuoso, xCelium, Incisive, vManager, IMC).
• Familiar with Verilog RTL coding and ASIC design methodology.
• Expert in SystemVerilog for assertions, constrained randomization, metric-driven verification, and UVM.
• Familiarity with behavioral modeling of analog blocks using SystemVerilog (RNM) and Verilog-AMS.
• Experience modeling mixed-signal blocks (bias networks, regulators, bandgaps, amplifiers, comparators, data converters, mixers, switches, multiplexers).
• Proficient in UNIX shell scripting and experience with Perl and TCL for automation.
• Proven experience writing verification plans, developing testbenches, running simulations, and debugging results.
• Demonstrated communication, cross-site collaboration, customer interaction, and people-management skills.

Nice-to-have:

• Experience modeling power converters.
• Prior experience managing budgets and resource planning for verification projects.

Education Requirements

Degree-level qualification expected: Bachelor's (or higher) in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or equivalent. The posting allows equivalent practical experience in lieu of a listed degree.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.