Senior STA Signoff Methodology Engineer

Job Title

Senior STA Signoff Methodology Engineer

Role Summary

Lead development and deployment of static timing analysis (STA) signoff strategies, flows, and tools to ensure timing, performance, yield, and reliability for high-performance GPUs, CPUs, LPUs and SoCs.

Work with technology, physical-design, and timing teams to model advanced-node physical effects and improve STA-to-silicon correlation through automation and data analysis.

Experience Level

Senior level — requires experienced engineers; the posting references ~8 years of ASIC design and timing experience.

Responsibilities

Primary responsibilities include building methodology, executing experiments, and producing analysis and automation for signoff at advanced nodes.

• Design, run, and analyze large-scale SPICE simulations and STA experiments to model timing impacts of advanced technologies.
• Develop STA and place-and-route recommendations addressing aging, self-heating, thermal effects, IR drop, electromigration, and other physical effects.
• Define and deploy timing-signoff strategies in collaboration with technology leads and physical-design teams.
• Create tools and methodologies to extend or augment standard EDA tool capabilities.
• Integrate STA, constraints, and timing/power optimization into signoff flows.
• Perform extensive data analysis to improve STA-to-silicon correlation and inform methodology decisions.

Requirements

Must-have technical skills and experience for successful candidates.

• Extensive experience in ASIC design and timing, including deep understanding of STA methodologies and EDA-tool limitations.
• Knowledge of RC extraction, device physics, and the mathematics/physics underlying electrical design.
• Experience with low-power techniques: multi-Vt, clock gating, power gating, activity-based power analysis, DVFS, and CDC considerations.
• Understanding of signal and power integrity topics: crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Familiarity with standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies (5 nm, 3 nm, 2 nm, or beyond).
• Practical experience with industry-standard tools such as PrimeTime, ICC2, RedHawk, Tempus, or equivalents.
• Strong communication skills and a collaborative working style.

Nice-to-have:

• Familiarity with 3D IC integration, die stacking/packaging, and self-heating effects on timing.
• Strong data-analysis and modeling skills (Python, JMP, or similar).
• Proficiency in Tcl and Python; C++ is a plus.

Education Requirements

MS in Electrical Engineering or Computer Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.