Senior STA Signoff Methodology Engineer

Job Title

Senior STA Signoff Methodology Engineer

Role Summary

Senior engineering role responsible for defining and deploying timing-signoff strategies and methodologies for high-performance GPUs, CPUs, LPUs and SoCs. The role focuses on improving performance, yield, and silicon reliability through modeling, analysis, and automation across multiple product lines.

Experience Level

Senior-level; expects approximately 8 years of ASIC design and timing experience.

Responsibilities

Key responsibilities include developing signoff flows, running experiments, and creating tools to improve timing predictability and silicon reliability.

• Run large-scale SPICE simulations and static timing analysis (STA) experiments to model advanced-node timing impacts.
• Develop STA and placement-and-routing (PNR) flows addressing aging, self-heating, thermal effects, IR drop, and electromigration.
• Collaborate with technology leads, physical-design engineers, and timing teams to define and deploy timing-signoff strategies.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond standard EDA capabilities.
• Work across STA, constraints, and timing and power optimization flows.
• Perform extensive data analysis to improve STA-to-silicon correlation using Python, JMP, or similar tools.

Requirements

Must-have technical skills and experience.

• 8+ years of experience in ASIC design and timing with hands-on signoff methodology work.
• Strong understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Solid foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques: multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
• Knowledge of signal and power integrity topics: crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Experience modeling standard-cell, memory, and I/O IP and their integration in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, or smaller nodes.
• Familiarity with industry-standard tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Strong communication skills and a collaborative working style.

Nice-to-have:

• Experience with 3D IC integration, die stacking, packaging, and their impact on timing closure and self-heating.
• Advanced data-analysis and modeling skills using Python, JMP, or similar platforms.
• Proficiency in Tcl and Python; C++ is a plus.

Education Requirements

MS in Electrical or Computer Engineering preferred, or equivalent practical experience. The posting also specifies approximately 8 years of relevant ASIC design and timing experience; equivalent professional experience may be accepted in lieu of the degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.