Senior STA Engineer, Sub-Chip

Role Summary

The role involves performing advanced Static Timing Analysis (STA) for chiplet and floor chip levels at NVIDIA's Networking team.

Experience Level

Mid-Level with at least 5 years of relevant experience.

Responsibilities

The main responsibilities include:

• Performing advanced Static Timing Analysis (STA) at the chiplet and floor chip level.
• Using Prime Time to review and debug timing paths, along with understanding constraints and SDC generation.
• Identifying convergence risks and collaborating with physical design, RTL, and DFT teams.
• Leading a full timing closure process and quality approval from pre-layout STA model through signoff.

Requirements

The essential qualifications are:

• B.SC./M.SC. in Electrical Engineering.
• 5+ years of hands-on STA experience.
• Experience with Prime Time and signoff methodologies.
• Strong leadership capabilities.

Education Requirements

Expected education is a B.SC. or M.SC. in Electrical Engineering.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.