Senior STA Engineer

Job Title

Senior STA Engineer

Role Summary

Member of the HIPD SAM team delivering end-to-end Static Timing Analysis (STA) and timing sign-off for Client, Server and ASIC Hard-IP portfolios and advanced test chips. Independently owns hands-on STA and timing closure for complex multi-GHz blocks and full-chip designs at advanced process nodes (3nm and below).

Experience Level

Senior-level — typically requires substantial industry experience. The posting specifies MS with ~10+ years or BS with ~12+ years of relevant STA experience.

Responsibilities

Primary responsibilities include ownership of STA flow, timing closure, methodology execution, automation, cross-team collaboration, and mentoring.

• Own block-level and full-chip STA from netlist handoff through final timing sign-off for multi-GHz designs.
• Drive timing closure across multiple modes, corners, and scenarios (MCMM).
• Define and own PVT corner definitions and extraction corner alignment.
• Lead and execute STA methodologies including POCVM, AOCV, and LVF.
• Define and apply timing margining and guard-band strategies for silicon robustness.
• Analyze and debug complex setup/hold, clocking, and constraint-related timing issues.
• Develop scripting and automation (TCL/Python) to improve analysis efficiency and quality.
• Partner with Physical Design, Logic, Clocking, and Methodology teams.
• Mentor junior engineers while remaining hands-on.

Requirements

Must-have technical skills and experience (degree and years-of-experience are listed under Education Requirements below).

• Proven silicon success closing timing on multi-GHz designs.
• Deep hands-on expertise with Synopsys STA tools, including PrimeTime and PTPX.
• Strong STA methodology knowledge: PVT corner definition, extraction corners, POCVM/AOCV/LVF, margining, and MCMM.
• Experience defining and applying timing margining and guard-band strategies.
• Skilled at analyzing and debugging setup/hold, clocking, and constraint-related issues.
• Strong scripting and automation skills in TCL and/or Python.
• Proven ability to collaborate with Physical Design, Logic, Clocking, and Methodology teams and to mentor junior engineers.

Education Requirements

BS with 12+ years of relevant STA experience OR MS with 10+ years of relevant STA experience. No specific fields of study or certifications were specified in the posting.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.