Senior STA Engineer

Role Summary

The Senior STA Engineer is responsible for the physical implementation of IP, Subsystem, or IC design, ensuring optimal performance and compliance.

Experience Level

Mid-level; 4-7 years of relevant experience required.

Responsibilities

The main responsibilities of the role include:

• Physical implementation of IP, Subsystem, or IC design.
• RTL synthesis setup, flow cleanup, performing experiments for optimization of area, timing, and power.
• Post-Scan Synthesis netlist STA timing checks and LEC flow setup.
• Timing convergence (STA) including related design and timing ECO.
• Understanding constraints, suggesting improvements to Design/DFT teams.
• Contributing to problem-solving related to physical design and defining best physical design strategies for each technology node.

Requirements

Key requirements for this position include:

• Proficiency in Synthesis and STA flow setup, specifically with Genus and Tempus flows.
• Experience with STA timing ECOs across multiple technology nodes.
• Strong understanding of constraints and clocks.
• Excellent communication skills and ability to work as a team player.

Education Requirements

Not specified.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.