Senior Speed and Reliability Codesign Engineer

Job Title

Senior Speed and Reliability Codesign Engineer

Role Summary

The Silicon Co-Design Group seeks an engineer to build and validate speed and reliability features in silicon, tying pre-silicon predictions to measured silicon and driving decisions across architecture, design, and manufacturing. The role works with architecture, VLSI, ASIC, firmware, and product teams to ensure chips meet frequency and lifetime targets.

Experience Level

Senior — typically 10+ years in silicon design, performance, timing, or post-silicon speed validation.

Responsibilities

Primary responsibilities include designing features, validating them in silicon, and using data-driven methods to accelerate correlation and verification.

• Design speed and reliability features from on-chip building blocks (on-die clocking, droop detection, aging monitors) that protect frequency and lifetime without extra power or margin.
• Own design-to-silicon correlation: compare VF curve, Vmin/Vmax, timing and aging margins between pre-silicon predictions and measured silicon, and feed discrepancies back to design.
• Verify codesign across voltage, temperature, process, and aging corners before tapeout.
• Develop AI/ML-driven flows for correlation, data analysis, and verification to reduce cycle time and find issues earlier.
• Quantify trade-offs across silicon-to-system boundaries (frequency, lifetime, power, yield, area) and present data-driven recommendations.
• Collaborate cross-functionally with architecture, design, manufacturing, firmware, and product teams.

Requirements

Must-have qualifications are listed first; additional strengths that improve candidacy are listed as nice-to-have.

• 10+ years of hands-on experience in silicon design, performance, timing, or post-silicon speed validation, with deep experience in timing and working with real silicon.
• Proven track record of taking features from concept through silicon validation with measured results.
• Design depth sufficient to implement features and strong data fluency to perform correlation against silicon; familiarity with silicon margining and guard-banding.
• Ability to influence cross-functional teams (architecture, design, manufacturing) without direct authority.
• Excellent problem-solving, collaboration, and interpersonal communication skills.

Nice-to-have:

• Experience closing the loop between predictions and silicon with a correlation methodology adopted by other teams.
• Experience designing or integrating on-die sensors/actuators (droop detectors, aging monitors, adaptive clocking, telemetry).
• Datacenter-scale or high-performance silicon experience.
• Applied ML or data-driven techniques for performance, reliability modeling, or design-space exploration.
• Patents, publications, or standards contributions in silicon performance or reliability.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

Additional Information

Locations include Santa Clara, CA; Austin, TX; and Hillsboro, OR. Position is hybrid. Base salary ranges by level are provided by the employer and total compensation includes equity and benefits. Applications accepted at least until 2026-07-11.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.