Senior SoC Subsystem and I/O Architect - LPU

Job Title

Senior SoC Subsystem and I/O Architect - LPU

Role Summary

Design and define high-level subsystem and I/O architecture for next-generation LPU AI and HPC SoC products. Work with IP, firmware, software, verification, and platform teams to convert product requirements into architecture and specification documents, models, and validation strategies.

Primary focus areas include PCIe/CXL, NVLink, UCIe, AXI/CHI, NoC fabrics, memory systems, coherency, boot/reset, firmware interfaces, RAS, power management, and platform initialization.

Experience Level

Senior-level (senior engineer). Typical background: 8+ years of relevant SoC/subsystem or interconnect architecture experience.

Responsibilities

Key responsibilities include:

• Define high-level SoC subsystem and I/O architecture for LPU products.
• Translate product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot/reset, safety, RAS, and power subsystems.
• Collaborate with IP teams to produce detailed build documents for PCIe/CXL, NVLink, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMU/IOMMU, and related infrastructure.
• Specify subsystem behaviors: enumeration, capability discovery, configuration flows, memory operation sequencing, address mapping, interrupts, virtualization, and error handling.
• Develop or guide functional/architectural models (C++, SystemC, Python) and use models to validate architecture intent before RTL/silicon availability.
• Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, and software usability.
• Review IP specs, subsystem docs, verification plans, and validation strategies; coordinate cross-team architecture decisions through to delivery.

Requirements

Must-have qualifications:

• 8+ years of hands-on experience in SoC architecture, subsystem/IO/interconnect architecture, or high-performance system architecture.
• Practical experience converting product requirements into architecture and IP/subsystem specifications.
• Deep knowledge of IO and interconnect cores (PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI) and/or NoC fabrics.
• Experience building functional/architectural/golden models (C++, SystemC, Python) from specifications and using them for validation.
• Strong understanding of memory ordering, coherency, address translation, interrupts, virtualization, MMU/IOMMU, and error management.
• Knowledge of boot/reset sequencing, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture.
• Strong written and verbal communication; proven ability to align architecture across IP, firmware, software, verification, and product teams.

Nice-to-have:

• Experience with LPU, GPU, CPU, AI accelerator, chiplet, or multi-die SoC architecture.
• Experience with post-silicon validation, DFT, secure boot, or power sequencing.
• Knowledge of deep learning workloads, numerics, and bandwidth/latency tradeoffs.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.