Senior SoC Physical Design Engineer, HBM

Job Title

Senior SoC Physical Design Engineer, HBM

Role Summary

Drive physical implementation of advanced high-bandwidth memory (HBM) system-on-chip (SoC) logic and base die designs from netlist through GDSII within the Heterogeneous Integration Group. Work hands-on to deliver performance, power, and area (PPA) targets and robust signoff collateral across block and top-level integration.

Collaborate closely with RTL design, verification, DFT, packaging, and manufacturing teams and support tapeout readiness and post-silicon debug.

Experience Level

Senior — typically 3–5+ years of related physical design or SoC implementation experience.

Responsibilities

Typical responsibilities for this role include:

• Implement SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet PPA targets.
• Assist with setup and hold timing closure across multi-mode, multi-corner (MMMC) scenarios using industry static timing tools.
• Collaborate with RTL and integration teams on clocking, reset strategies, and power intent implementation.
• Integrate complex IP blocks (controllers, interfaces, MBIST, DFT logic, PHY-adjacent logic) with focus on timing and physical correctness.
• Run and debug physical signoff checks (DRC, LVS) and address violations with signoff experts.
• Work with DFT teams to ensure scan and MBIST logic are physically clean and do not harm timing or routability.
• Participate in tapeout readiness activities including ECO flows, checklists, design reviews, and post-silicon debug by correlating silicon behavior with physical design and analysis.
• Develop and apply hands-on EDA tool workflows and automation while working in a cross-functional, global team.

Requirements

Key technical requirements and preferred skills.

• Must-have: Hands-on experience with EDA physical design and signoff tools such as Innovus, Fusion Compiler, IC Validator (ICV), or Calibre.
• Must-have: Solid understanding of static timing analysis fundamentals, clocking concepts, and Synopsys Design Constraints (SDC).
• Must-have: Working knowledge of power intent methodologies (UPF or CPF), power grid planning, and basic power integrity considerations.
• Must-have: Familiarity with physical verification and signoff flows (DRC, LVS) and parasitic awareness.
• Must-have: Experience with hierarchical physical design and SoC integration methodologies.
• Nice-to-have: Experience with HBM or DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Nice-to-have: Experience with signal integrity and reliability analysis (IR drop, electromigration) and tools such as Ansys.
• Nice-to-have: Experience scripting in Tcl or Python to automate checks, reporting, and flow improvements.
• Nice-to-have: Familiarity with PrimeTime or Tempus for timing analysis and experience with ECO/tapeout flows and post-silicon correlation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.