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Senior SoC Physical Design Engineer

Qualcomm
September 22, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Senior

Job Title

Senior SoC Physical Design Engineer

Role Summary

Design and deliver SoC physical implementation: synthesis, place-and-route, sign-off convergence and optimizations to meet power, performance, and area (PPA) targets. Work with RTL, IP, verification, and tapeout teams to integrate IP, resolve timing and manufacturability issues, and drive physical design automation and process-porting for advanced technology nodes.

Experience Level

Senior - typically requires substantial prior hardware/physical-design experience. The posting lists experience guidance: Bachelor's +6+ years; Master's +5+ years; PhD +4+ years in Hardware Engineering or related fields. (The posting also contains a line referencing 2–4 years of physical design experience.)

Responsibilities

Primary responsibilities include:

  • Lead synthesis, place-and-route (PnR) and sign-off convergence activities for complex SoC subsystems.
  • Perform Static Timing Analysis (STA) and implement sign-off timing optimizations.
  • Drive PPA optimizations across the design flow to meet performance, power, and area targets.
  • Implement low-power design techniques including UPF, multi-voltage domains, and power gating.
  • Integrate IP blocks and resolve integration and floorplanning issues across the SoC.
  • Collaborate with RTL, verification, manufacturing, and CAD teams during bring-up and tapeout.
  • Develop and apply automation to improve physical design productivity and outcomes.
  • Port and optimize designs for advanced process technology nodes and multiple timing/operating points.

Requirements

Must-have technical skills and experience:

  • Proven experience in synthesis, PnR, sign-off convergence, and STA-driven optimizations.
  • Experience meeting demanding PPA requirements for complex sub-systems / SoCs.
  • Hands-on experience with low-power implementation flows (UPF, multi-voltage, power gating).
  • Familiarity with ASIC physical-design flows and methodologies; understanding of device physics and deep sub-micron effects.
  • Experience working on advanced technology nodes and multiple target operating points.
  • Ability to drive automation efforts to improve PPA and flow efficiency.

Education Requirements

The posting specifies: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of hardware-engineering experience; OR Master's degree in those fields with 5+ years; OR PhD in those fields with 4+ years. The posting also includes one line mentioning a Bachelor's in Electrical/Electronics Engineering with 2–4 years of physical-design experience.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-22