Senior SoC Integration Engineer

Role Summary

The Senior SoC Integration Engineer role at AMD involves participating in the SoC Physical Integration team to ensure the successful physical and electrical verification of AMD’s SoC FPGA/ACAP devices. This position requires collaboration with various engineering teams focusing on integrating and optimizing chip design processes.

Experience Level

This is a mid-career position, suitable for individuals with relevant experience in FPGA/ACAP design and integration.

Responsibilities

• Define and develop flows and methodologies for chip-level integration.
• Create tools for design verification and improve efficiency in design processes.
• Design and verify FPGA/ACAP sub-blocks through RTL and custom designs.
• Coordinate with different design groups to maintain smooth integration across efforts.
• Execute chip-level physical and electrical verification to ensure design integrity.

Requirements

• Basic understanding of FPGA architecture.
• Familiarity with design and verification tools such as Virtuoso and Calibre.
• Experience with Place and Route (P&R) tools.
• Fundamental circuit design knowledge and simulation experience with Spice and Verilog.
• Strong debugging skills and scripting experience in Perl, Python, TCL, or other scripting languages.
• Proficiency in Unix data management and job control.
• Excellent written and oral communication skills.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering is required, along with FPGA working experience.