Senior SoC Design Engineer (Hardware)

Job Title

Senior SoC Design Engineer (Hardware)

Role Summary

Design SoC architecture, micro-architecture and RTL for AI accelerator chips. Work within the Hardware team in Seoul to deliver production-ready silicon through architecture decisions, RTL development, integration, and cross-team collaboration.

Experience Level

Senior — see Education Requirements for degree-specific years-of-experience guidance.

Responsibilities

Deliver SoC-level and block-level design from architecture through silicon bring-up; coordinate with verification, physical implementation, and bring-up teams.

• Decide and evaluate optimal SoC architecture based on requirements and performance targets.
• Define micro-architecture and produce RTL for blocks and subsystems.
• Perform top-level integration, timing closure, lint checks and synthesis; collaborate with other teams to resolve integration issues.
• Create verification plans and work with Design Verification to achieve coverage goals.
• Coordinate with Physical Implementation (PnR) to anticipate and address physical design constraints in RTL.
• Participate in silicon bring-up and system-level verification activities.

Requirements

Core technical skills and experience required; preferred skills listed separately.

• Proven RTL design and micro-architecture experience for complex digital blocks and subsystems.
• Experience with top-level integration, timing closure, synthesis and lint flows.
• Track record of cross-team collaboration with verification, physical implementation and bring-up teams.
• Practical experience using EDA tools such as verification engines, synthesis tools and power/area estimation tools.
• Strong documentation and communication skills to convey architecture and design intent.

Nice-to-have:

• SoC System IP design and chip-top integration experience.
• Subsystem/top-level design for data-center or large-scale SoCs.
• FPGA prototyping/porting experience.
• Deep understanding of AMBA bus protocols, other bus interfaces, and clock-domain crossing (CDC) techniques.
• Experience with design automation, scripting and design-flow improvements.

Education Requirements

Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science or a related technical field (7+ years of RTL design experience); or a Master’s degree in those fields (5+ years of RTL design experience). No certifications or equivalent-experience language explicitly stated.

About the Company

Company: FuriosaAI

Headquarters: Seoul, South Korea

FuriosaAI develops high-performance, energy-efficient AI inference hardware and software. Founded in 2017 by semiconductor and AI engineers, the company builds AI-native compute platforms to reduce AI energy and operational costs and operates globally with offices in Korea, Silicon Valley, and an R&D lab in Lisbon.