Senior Silicon Power Engineer

Job Title

Senior Silicon Power Engineer

Role Summary

Owner for power-feature productization on a flagship silicon program within the Silicon Power Team. Lead cross-functional technical efforts to characterize, validate, debug, and productize power and low-power capabilities across architecture, firmware, validation, software, and production.

Primary focus areas: close complex multi-functional power failures quickly and build AI-enabled characterization workflows that scale and can be trusted for production decisions.

Experience Level

Senior-level. Role expects demonstrated post-silicon ownership and leadership; typical candidates have multiple years of industry experience in silicon bring-up and power productization.

Responsibilities

Technical ownership and hands-on execution to ensure power features work reliably at scale.

• Lead cross-functional execution of power and low-power productization strategy across architecture, validation, firmware, software, and production teams.
• Characterize and validate new power-saving features; design measurements and lab experiments to verify behavior.
• Debug complex silicon power issues, develop hypotheses and measurement plans, and drive root-cause closure with productized fixes.
• Design and deploy AI-enabled workflows for analysis of characterization, telemetry, and shmoo data with guardrails and measurable impact.
• Act as key technical owner for multi-disciplinary tradeoffs involving power, thermal, performance, firmware, and schedule constraints.
• Collaborate with global teams including system architects, chip/board designers, SW/FW engineers, reliability, ATE, and program management.

Requirements

Must-have technical skills and demonstrated impact required for the role.

• Proven track record in post-silicon bring-up and validation of silicon power features on complex ASIC or SoC programs (hands-on, not purely coordination).
• Deep hands-on expertise in power-saving mechanisms, power characterization, tester-to-system correlation, and lab fundamentals (oscilloscopes, DMM, DAQ, debuggers).
• Ability to resolve ambiguous, cross-boundary issues across architecture, firmware, validation, and platform and to codify fixes as reusable methodology.
• Demonstrated experience building or scaling AI-enabled workflows for silicon characterization or validation with observable adoption and validation discipline.
• Strong end-to-end understanding of silicon behavior and ability to make tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.

Nice-to-have:

• Subsystem expertise in Windows and Linux low-power states, transistor/device physics, silicon reliability, and aging mechanisms.
• Evidence of silicon-level impact you personally drove (faster bring-up, methodology improvements, patents, or published work).
• Experience deploying agentic or production-scale ML/RAG workflows for characterization analytics or automated trend detection.
• Experience partnering with engineering counterparts across geographies with shared on-call and shared metrics.

Education Requirements

BS plus ~5 years post-degree experience, or MS plus ~4 years post-degree experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.