Senior Silicon Physical Design and Layout Engineer

Job Title

Senior Silicon Physical Design and Layout Engineer

Role Summary

Design and implement physical layout for mixed-signal and digital ASICs used in a space-based communications system. The role focuses on floorplanning, power distribution, timing closure, physical verification, and manufacturability for high-reliability satellite electronics.

This position sits on a hardware/ASIC implementation team delivering space-qualified, high-performance silicon; occasional travel and on-site work at one of the company's U.S. engineering sites are expected.

Experience Level

Senior — typically 7+ years of relevant physical design and layout experience.

Responsibilities

Primary implementation and verification duties for ASIC physical design and post-silicon validation.

• Execute physical design and detailed layout for complex mixed-signal and digital ASICs integrating analog and digital blocks.
• Perform floorplanning, power distribution network design, clock tree synthesis, and signal routing.
• Perform timing closure, static timing analysis, and signal integrity analysis; resolve timing violations.
• Run physical verification including DRC, LVS, and ERC and iterate with designers to meet foundry rules.
• Optimize layouts for manufacturability, yield, radiation tolerance, and reliability in space environments.
• Implement design-for-test (DFT) structures and participate in testability planning.
• Collaborate with front-end designers to preserve design intent through implementation and handoff.
• Work with foundries on process design rules, tapeout readiness, and yield optimization.
• Support post-silicon validation, debug, and performance optimization activities.
• Document physical design processes, results, and lessons learned.

Requirements

Must-have technical skills and experience for day-one competency.

• 7+ years of experience in physical design and layout of ASICs.
• Demonstrated expertise in digital and analog layout techniques for complex SoCs or ASICs.
• Practical experience with industry-standard physical design EDA tools (Cadence, Synopsys, Mentor).
• Knowledge of semiconductor fabrication processes, foundry design rules, and tapeout flow.
• Proven experience with timing closure, static timing analysis, and signal integrity debugging.
• Experience with power analysis and optimization, PDN design, and low-SWaP implementation considerations.

Nice-to-have skills and domain knowledge.

• Mixed-signal and RF layout techniques.
• Experience with radiation-hardened or high-reliability design methodologies.
• Experience with advanced process nodes (16 nm and below) and high-speed digital design (>1 GHz).
• Familiarity with 3D packaging, chiplets, thermal design considerations, and low-power techniques.
• Prior work on space-qualification requirements or aerospace electronics.

Education Requirements

Bachelor's degree (B.S.) in Electrical Engineering, Computer Engineering, or a related technical field is required. Advanced degrees (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, or related fields are listed as preferred.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.