Senior Silicon Physical Design and Layout Engineer

Job Title

Senior Silicon Physical Design and Layout Engineer

Role Summary

Design and implement physical layouts for mixed-signal ASICs and RF processing chips used in space-based communications. Work on floorplanning, power distribution, clock tree synthesis, routing, timing closure, and physical verification to meet space qualification, reliability, and manufacturability requirements.

Position is based on-site in Austin, TX; San Diego, CA; the Bay Area, CA; or Renton, WA. Relocation assistance is provided; travel up to 10% is expected. Interviews include a technical assessment.

Experience Level

Senior — requires 7+ years of relevant experience in physical design and layout of ASICs.

Responsibilities

Primary responsibilities include:

• Execute physical design and layout for complex mixed-signal ASICs that integrate analog and digital processing.
• Develop and implement floorplanning, power distribution networks, clock tree synthesis, and routing strategies.
• Perform timing closure, signal integrity analysis, and static timing analysis; address timing violations.
• Run and resolve physical verification checks (DRC / LVS / ERC) and ensure design rule compliance.
• Optimize layouts for radiation tolerance, reliability, thermal constraints, and reduced size/weight/power (SWaP).
• Collaborate with front-end designers to preserve design intent through implementation and with foundries to ensure manufacturability and yield.
• Implement design-for-test (DFT) structures and support post-silicon validation and debug activities.
• Use data analytics to drive ASIC performance improvements and document physical design processes and results.

Requirements

Must-have skills and experience (concise):

• 7+ years experience in physical design and layout of ASICs (mixed-signal and digital/analog integration).
• Demonstrated expertise in digital and analog layout techniques.
• Hands-on experience with industry-standard EDA tools for physical design (Cadence, Synopsys, Mentor).
• Knowledge of semiconductor fabrication processes and design rules; experience working with foundries for manufacturability and yield optimization.
• Proven experience with timing closure, signal integrity, static timing analysis, and power analysis/optimization.
• Experience with physical verification (DRC/LVS/ERC) and design-for-test (DFT) methodologies.
• Ability to support post-silicon validation and debug.

Nice-to-have / preferred:

• Experience with mixed-signal or RF layout techniques.
• Knowledge of radiation-hardened design methodologies and space qualification requirements for electronic components.
• Experience with advanced process nodes (16 nm and below) and high-speed digital design (>1 GHz).
• Familiarity with 3D packaging or chiplet technologies and thermal considerations in ASIC design.
• Experience with low-power design techniques for battery- or solar-powered systems.

Education Requirements

Minimum: B.S. in Electrical Engineering, Computer Engineering, or a related field. Preferred: advanced degree (MS or PhD) in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.