Senior Silicon Physical Design and Layout Engineer

Job Title

Senior Silicon Physical Design and Layout Engineer

Role Summary

Design and implement physical layout for mixed-signal ASICs that support a space-based communications satellite network (TeraWave). Work includes floorplanning, power distribution, clock tree synthesis, routing, verification, and post-silicon validation to meet space-qualification and low size/weight/power requirements.

This role is part of the ASIC/hardware engineering team and collaborates with front-end designers, foundries, test teams, and cross-functional engineering groups. Position is on-site at a U.S. engineering location.

Experience Level

Senior — requires 7+ years of relevant experience in ASIC physical design and layout.

Responsibilities

Primary responsibilities include:

• Execute physical design and layout of mixed-signal ASICs integrating analog, digital, and RF blocks.
• Perform floorplanning, power-distribution network design, clock tree synthesis, placement, and routing for complex designs.
• Perform timing closure, static timing analysis, and signal integrity analysis; resolve timing violations.
• Run physical verification (DRC/LVS/ERC) and ensure manufacturability with foundry rules.
• Optimize layouts for radiation tolerance, reliability, thermal constraints, and SWaP requirements in space environments.
• Implement design-for-test (DFT) structures and support post-silicon validation, debug, and yield optimization.
• Collaborate with front-end designers to preserve design intent and use data-driven methods to optimize ASIC performance.
• Coordinate with semiconductor foundries to ensure manufacturability and drive yield improvements.

Requirements

Must-have:

• 7+ years of physical design and layout experience for ASICs, including mixed-signal designs.
• Proven expertise in digital and analog layout techniques and complex mixed-signal implementation.
• Experience with industry-standard EDA physical-design tools (Cadence, Synopsys, or Mentor).
• Knowledge of semiconductor fabrication processes, design rules, timing closure, signal integrity, and power-analysis/optimization techniques.
• Experience with physical verification flows (DRC/LVS/ERC) and static timing analysis.
• Ability to work on-site at a U.S. engineering location; up to 10% travel expected. Relocation provided.
• Must meet export-control eligibility: U.S. citizen, U.S. national, U.S. permanent resident (Green Card), or lawfully admitted refugee/asylee.

Nice-to-have:

• Experience with RF/mixed-signal layout techniques and radiation-hardened design methodologies.
• Advanced process-node experience (16nm and below), high-speed digital (>1 GHz), 3D packaging or chiplet technologies.
• Familiarity with space qualification requirements, thermal considerations, low-power design, and yield/manufacturability optimization.
• Advanced degree (M.S. or Ph.D.) in a relevant field.

Education Requirements

Required: B.S. in Electrical Engineering, Computer Engineering, or a related field. Preferred: M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.