Senior Silicon Architect – Cache Coherent Interconnects
NVIDIAJob Title
Senior Silicon Architect – Cache Coherent Interconnects
Role Summary
Member of the CPU Cache Coherent Interconnects Design Team responsible for silicon architecture and construction planning for next-generation CPU processors. Focus areas include dielet partitioning, packaging and die-stacking exploration, floorplanning, and die-to-die interface planning.
Experience Level
Senior-level. Requires 8+ years of experience in processor or other related high-performance semiconductor designs.
Responsibilities
The role owns silicon architecture and implementation planning across multi-die constructions and works with cross-functional teams to meet performance, power, and thermal goals.
- Own silicon architecture and construction plan for next-generation CPU processors.
- Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions and determine placement of I/O, CPU cores, caches, and NOC across dielets.
- Develop early floorplans and plan die-to-die and off-chip I/O (including UCIe, DRAM and PCIe).
- Coordinate with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal targets.
- Analyze on-die and cross-die wire densities and their impact on floorplanning and timing.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- 8+ years of experience in processor or other related high-performance semiconductor designs.
- Deep understanding of digital design, CPU system architecture, and ASIC floorplanning, including wire density considerations on single dies and 3D-connected dies.
- Experience planning die-to-die and off-chip I/O (e.g., UCIe, DRAM, PCIe) and developing early floorplans.
- Proven ability to work cross-functionally with architecture, logic, physical design, and packaging teams; strong communication and interpersonal skills.
- Nice-to-have: background in cache coherency or high-speed interconnects and familiarity with industry coherency/IO/memory protocols.
- Nice-to-have: knowledge of advanced packaging technologies (e.g., TSMC InFO, CoWoS, Intel EMIB), through-silicon via configurations, backside power delivery, interposer/substrate connectivity, and dielet concepts.
Education Requirements
Master's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
