Senior Signal Integrity Engineer

Job Title

Senior Signal Integrity Engineer

Role Summary

Lead end-to-end signal integrity (SI) for a multi-die AI accelerator: from die and package through board and system channel. The role includes architectural influence on interfaces, stackups and channel definition rather than only verification of closed specs.

Position is based in Barcelona with a hybrid cadence (4 days in office, 1 day WFH) and involves close cross-functional work with package, PHY/IP, DRAM and system teams.

Experience Level

Senior - 8+ years of experience in signal integrity for high-speed digital systems, including package-level SI.

Responsibilities

Deliver SI solutions spanning die, package, board and channel and drive vendor and validation activities.

• Define and enforce loss, crosstalk and jitter budgets across die, package, board and system channel; run pre-layout feasibility studies to influence routing, stackup and layer assignment.
• Perform 3D full-wave and hybrid extraction of package and board structures; define port and reference conventions for simulations.
• Run statistical and time-domain channel simulations (IBIS-AMI, FEC-aware for Gen6) and interpret results for compliance and margining.
• Ensure model quality: passivity, causality, reciprocity and DC accuracy for models entering the flow.
• Specify SI requirements for package vendors/OSATs and drive model and characterization requirements with IP, PHY, DRAM and package vendors.
• Correlate simulation with measurements (VNA, TDR, on-die margin scans) and support board bring-up and validation.
• Own SI for system-level elements: backplane, connectors, cabling and rack-scale channel considerations.

Requirements

Must-have technical skills and experience.

• 8+ years' experience in signal integrity for high-speed digital systems, including package-level work.
• Hands-on experience with a 3D EM extraction suite (Ansys HFSS/SIwave, Cadence Clarity/Sigrity, Keysight or equivalent).
• Proven SI closure on multi-gigabit SerDes (PCIe Gen5/Gen6 or comparable) and wide parallel memory interfaces (DDR5, LPDDR5/6 or HBM).
• Working knowledge of IBIS, IBIS-AMI and channel simulation methodology.
• Ability to read and reason from package substrate stackups and bump maps.
• Python scripting for automation and post-processing.

Nice-to-have:

• Silicon package co-design experience (2.5D, interposer, chiplet, advanced substrate).
• Material characterization and measurement correlation experience.
• Familiarity with OCP rack-scale platforms and high-speed connector systems.
• Experience with automated or AI-assisted engineering flows (PyAEDT, scikit-rf, etc.).

Education Requirements

Not specified.

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.