Senior Serdes System Design Engineer/Architect
BroadcomJob Title
Senior Serdes System Design Engineer/Architect
Role Summary
Design and validate high-speed Serdes physical-layer algorithms and system architectures for wireline communication products. Work within a cross-disciplinary ASIC design team to implement signal-processing algorithms in silicon and to verify performance in lab and production environments.
Collaborate with analog and digital designers, DVT/lab engineers, and standards bodies to deliver production-ready Serdes solutions at 100G+ data rates.
Experience Level
Senior — typically 10–12+ years of relevant experience in communication systems, DSP, or Serdes/system design.
Responsibilities
Primary responsibilities include:
- Develop channel models and run simulations to define Serdes architecture.
- Define and document signal-processing block requirements, architecture, and lab test plans.
- Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
- Develop and run system-level simulation suites to evaluate architectural tradeoffs.
- Work with design teams to perform vector-matching verification with RTL simulations.
- Develop, test, and debug firmware associated with physical-layer functionality.
- Perform lab testing and debug of Serdes devices to prepare for high-volume production.
- Produce documentation and application notes; provide customer support and technical input to marketing.
- Contribute to standards development (e.g., IEEE, OIF) relevant to next-generation wireline communications.
Requirements
Must-have technical skills and experience:
- Expert knowledge of communication theory and digital signal processing algorithms.
- Expert proficiency in MATLAB and C/C++ for algorithm development and modeling.
- Working knowledge of analog circuit behavior and transmission-line theory (s-parameters).
- Hands-on laboratory skills for testing and debugging high-speed Serdes.
- Experience with system-level simulation and verification, and familiarity with RTL interactions and vector matching.
- Firmware development and debugging for physical-layer functionality.
Nice-to-have:
- Experience designing high-speed Clock and Data Recovery (CDR) PLLs.
- Experience with equalization techniques for wireline/read-channel applications.
- RTL coding experience.
- Knowledge of IEEE 802.3 / OIF 100G/200G/400G Serdes and PCIe Gen6/Gen7 standards.
Education Requirements
B.S. in Electrical Engineering with 12+ years relevant experience, or M.S. in Electrical Engineering with 10+ years relevant experience.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
